diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-20 19:57:40 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-22 00:35:33 +0000 |
| commit | 5e2d9c0979696e63822854432cd37e9ea2189e99 (patch) | |
| tree | 61c0b2d39535a8b6aa3728c549df387ba785caf8 /src/soc/amd/stoneyridge/acpi/globalnvs.asl | |
| parent | 4a5f2e9e968d8e0b6f2e5c5a041897f5115fa385 (diff) | |
soc/amd/stoneyridge: clean up global NVS
Remove the unused fields that were previously used for PCNT and PWRS.
The LIDS field is only used in the ACPI code, but keep if for now, since
it would require a bigger rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b172214998818f841f5694f47815eddfaf9deaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72139
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/globalnvs.asl')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/globalnvs.asl | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index e60789ec84..703e16f58c 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -9,15 +9,13 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - , 8, // 0x00 - Processor Count - LIDS, 8, // 0x01 - LID State - , 8, // 0x02 - AC Power State - CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console - PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index - GPEI, 64, // 0x0f - 0x16 - GPE Wake Source - TMPS, 8, // 0x17 - Temperature Sensor ID - TCRT, 8, // 0x18 - Critical Threshold - TPSV, 8, // 0x19 - Passive Threshold + LIDS, 8, // 0x00 - LID State + CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console + PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index + GPEI, 64, // 0x0d - 0x14 - GPE Wake Source + TMPS, 8, // 0x15 - Temperature Sensor ID + TCRT, 8, // 0x16 - Critical Threshold + TPSV, 8, // 0x17 - Passive Threshold Offset (0x20), // 0x20 - AOAC Device Enables , 5, IC0E, 1, // I2C0, 5 |