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authorSubrata Banik <subratabanik@google.com>2023-09-02 19:16:52 +0000
committerSubrata Banik <subratabanik@google.com>2023-09-04 05:37:15 +0000
commit1b96bff27ea98593f28e1bd60b3ee8e727841d2a (patch)
treecf9e05b8dc6c7a86be2bbeaffec07bee6ec6d367 /src/soc/amd/picasso
parent5c35d30ffc7382af46b62044a5cf5326b1e57708 (diff)
{drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` config
This patch renames `SAVE_MRC_AFTER_FSPS` config to `FSP_NVS_DATA_POST_SILICON_INIT` to highlight the violation in the Xeon SP FSP implementation, where the FSP Silicon Init API produces Non-Volatile Storage (NVS) instead of the FSP-Memory Init API. According to the FSP 2.x specification (section 11.3), the FSP populates the NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and expects the boot firmware to parse the FSP_NON_VOLATILE_STORAGE_HOB after the FspMemoryInit() API in API mode. However, not all Intel SoC platforms that support the FSP 2.x specification adhere to this requirement. For example, the FSP binary for XEON SP platform produces NVS data (aka FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() API. Therefore, attempting to locate NVS data after the FspMemoryInit() API on these platforms would result in an error. The `save_mrc_data.c` implementation provides the required hooks to locate the NVS post FSP-Silicon Init and store into Non-Volatile Storage. BUG=b:296704537 TEST=Able to build and boot Intel Xeon SP w/o any functional impact. Change-Id: I815a64263fa1415bfe30bb3c1c35e4adee307e86 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
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