{drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` config

This patch renames `SAVE_MRC_AFTER_FSPS` config to
`FSP_NVS_DATA_POST_SILICON_INIT` to highlight the violation in the Xeon
SP FSP implementation, where the FSP Silicon Init API produces
Non-Volatile Storage (NVS) instead of the FSP-Memory Init API.

According to the FSP 2.x specification (section 11.3), the FSP
populates the NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and
expects the boot firmware to parse the FSP_NON_VOLATILE_STORAGE_HOB
after the FspMemoryInit() API in API mode.

However, not all Intel SoC platforms that support the FSP 2.x
specification adhere to this requirement. For example, the FSP binary
for XEON SP platform produces NVS data (aka
FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() API.
Therefore, attempting to locate NVS data after the FspMemoryInit() API
on these platforms would result in an error. The `save_mrc_data.c`
implementation provides the required hooks to locate the NVS post
FSP-Silicon Init and store into Non-Volatile Storage.

BUG=b:296704537
TEST=Able to build and boot Intel Xeon SP w/o any functional impact.

Change-Id: I815a64263fa1415bfe30bb3c1c35e4adee307e86
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

3 files changed, 19 insertions, 6 deletions

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index f5399ea92c..ca17bc7c60 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -410,13 +410,26 @@ config FSP_ENABLE_SERIAL_DEBUG
 	  coreboot native debug driver when coreboot has integrated the debug FSP
 	  binaries. coreboot disables serial messages when this config is not enabled.
 
-config SAVE_MRC_AFTER_FSPS
+config FSP_NVS_DATA_POST_SILICON_INIT
 	bool
 	default n
-	depends on XEON_SP_COMMON_BASE
 	help
-	  Save MRC training data after FSP-S. Select this on platforms that generate MRC
-	  cache HOB data as part of FSP-S rather than FSP-M.
+	  Select this config to enable the workaround for Intel SoC platforms that
+	  do not adhere to the FSP 2.x specification requirement, where the FSP
+	  Silicon Init API produces Non-Volatile Storage (NVS) data instead of the
+	  FSP-Memory Init API.
+
+	  According to the FSP 2.x specification (section 11.3), the FSP populates the
+	  NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and expects the boot firmware
+	  to parse the FSP_NON_VOLATILE_STORAGE_HOB after the FspMemoryInit() API in API
+	  mode.
+
+	  However, not all Intel SoC platforms that support the FSP 2.x specification
+	  adhere to this requirement. For example, the FSP binary for XEON SP platform
+	  produces NVS data (aka FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit()
+	  API. Therefore, attempting to locate NVS data after the FspMemoryInit() API on
+	  these platforms would result in an error. Use this config to find the NVS data
+	  and store it in Non-Volatile Storage after the FspSiliconInit() API.
 
 config FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
 	bool
diff --git a/src/drivers/intel/fsp2_0/save_mrc_data.c b/src/drivers/intel/fsp2_0/save_mrc_data.c
index 19e8a52cff..1d682b99c2 100644
--- a/src/drivers/intel/fsp2_0/save_mrc_data.c
+++ b/src/drivers/intel/fsp2_0/save_mrc_data.c
@@ -46,7 +46,7 @@ static void save_mrc_data(void *unused)
  * Should be done before ramstage_cse_fw_sync() to avoid traning memory twice on
  * a cold boot after a full firmware update.
  */
-#if CONFIG(SAVE_MRC_AFTER_FSPS)
+#if CONFIG(FSP_NVS_DATA_POST_SILICON_INIT)
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, save_mrc_data, NULL);
 #else
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, save_mrc_data, NULL);
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 9c19f3b1cc..dac093f9d2 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -2,8 +2,8 @@
 
 config SOC_INTEL_SAPPHIRERAPIDS_SP
 	bool
+	select FSP_NVS_DATA_POST_SILICON_INIT
 	select MICROCODE_BLOB_NOT_HOOKED_UP
-	select SAVE_MRC_AFTER_FSPS
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select DISABLE_ACPI_HIBERNATE
 	select DEFAULT_X2APIC_RUNTIME