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authorFelix Held <felix-coreboot@felixheld.de>2023-06-01 21:56:39 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-06-07 00:26:57 +0000
commit78381094b20d1af933f369505910b4f5f2954895 (patch)
tree320c2a29b2c14995202f8b43bdd0c9b5d4754298 /src/soc/amd/picasso/acpi/soc.asl
parentc79c64be95822070ad1a74056356ffe65530df1b (diff)
soc/amd/picasso/acpi: move remaining parts of sb_pic0_fch.asl to soc.asl
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785abfc90c99b58c11d57847573f550fcea1f774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/picasso/acpi/soc.asl')
-rw-r--r--src/soc/amd/picasso/acpi/soc.asl3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index 82c2766e33..0b520e42a9 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -9,7 +9,8 @@ Scope(PCI0) {
#include "northbridge.asl"
/* Describe the AMD Fusion Controller Hub */
- #include "sb_pci0_fch.asl"
+ #include <soc/amd/common/acpi/lpc.asl>
+ #include <soc/amd/common/acpi/platform.asl>
}
/* PCI IRQ mapping for the Southbridge */