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-rw-r--r--src/soc/amd/picasso/acpi/sb_pci0_fch.asl8
-rw-r--r--src/soc/amd/picasso/acpi/soc.asl3
2 files changed, 2 insertions, 9 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
deleted file mode 100644
index ead676dde0..0000000000
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* System Bus */
-/* _SB.PCI0 */
-
-/* 0:14.3 - LPC */
-#include <soc/amd/common/acpi/lpc.asl>
-#include <soc/amd/common/acpi/platform.asl>
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index 82c2766e33..0b520e42a9 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -9,7 +9,8 @@ Scope(PCI0) {
#include "northbridge.asl"
/* Describe the AMD Fusion Controller Hub */
- #include "sb_pci0_fch.asl"
+ #include <soc/amd/common/acpi/lpc.asl>
+ #include <soc/amd/common/acpi/platform.asl>
}
/* PCI IRQ mapping for the Southbridge */