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authorVarshit Pandya <pandyavarshit@gmail.com>2023-10-16 22:56:52 +0530
committerFelix Held <felix-coreboot@felixheld.de>2023-10-31 14:40:22 +0000
commit5397b4dcf228b097f769fcaf3d88cc36316423c1 (patch)
tree76474734208246a26f50e689c3053edef5c6c20d /src/soc/amd/genoa/acpi/soc.asl
parentd581878264fc9c5900c19d1a8b3b1851d1b695db (diff)
soc/amd/genoa: Add PCI interrupt support
This patch adds PCI interrupt details as per the Processor Programming Reference (PPR) version 0.25 (#55901), table 319. Change-Id: I81251bd60aac1d7bd3181699d3adca315291f336 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78392 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/genoa/acpi/soc.asl')
-rw-r--r--src/soc/amd/genoa/acpi/soc.asl6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/acpi/soc.asl b/src/soc/amd/genoa/acpi/soc.asl
new file mode 100644
index 0000000000..88b0df81c8
--- /dev/null
+++ b/src/soc/amd/genoa/acpi/soc.asl
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include "pci_int_defs.asl"
+} /* End \_SB scope */