diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-05 08:05:45 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-09 14:37:33 +0000 |
| commit | cbf957158806bcd5c733c45baa324559904c609c (patch) | |
| tree | 89649e264f785ceb76ce223094b3640135a1b920 /src/northbridge | |
| parent | 2a0e3b25ea282491cba9d32a8f35d9a238db83c7 (diff) | |
drivers/pc80/rtc: Separate {get|set}_option() prototypes
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/gm45/igd.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/gma.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/early_init.c | 2 |
7 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index b1ce1bef90..cfd067e044 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include "gm45.h" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 6e650eb050..1deca3eeba 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <cbmem.h> #include <romstage_handoff.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <types.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index d08b77d3e2..98e30e7d07 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -22,7 +22,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <edid.h> #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 215e9b82cb..7735522da9 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -24,7 +24,7 @@ #include <cbmem.h> #include <cf9_reset.h> #include <ip_checksum.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <device/pci_def.h> #include <device/device.h> #include <halt.h> diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index b5c5ee0f63..c3cd380dc5 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -20,7 +20,7 @@ #include <device/pci.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <types.h> #define LPC PCI_DEV(0, 0x1f, 0) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 95fc52d262..74ae4f5e08 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -21,7 +21,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <romstage_handoff.h> #include <types.h> diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index c9d44fc8d5..3520b88deb 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -22,7 +22,7 @@ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */ #endif -#include <pc80/mc146818rtc.h> +#include <option.h> #include "x4x.h" #include <console/console.h> #include <romstage_handoff.h> |