diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2022-01-26 08:01:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 14:48:56 +0000 |
| commit | 921b99ed4bb988b61ce42d14204564adebaed662 (patch) | |
| tree | 2ee2123f58bc5d462017035019d2bc15825c1697 /src/northbridge | |
| parent | a233eb4b0a92c56e2d91a533b96bafbdf0413c9c (diff) | |
nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macros
Change-Id: Icca870d1c97a2737dec3f31b0f2e4c3222c711ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 4027708617..8b5619cfb3 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -5,6 +5,7 @@ #include <cf9_reset.h> #include <string.h> #include <device/device.h> +#include <device/dram/ddr3.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cbmem.h> @@ -422,14 +423,14 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = 0; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][122], - sizeof(uint8_t) * 4); + &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], + sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][128], - sizeof(uint8_t) * 18); + &pei_data->spd_data[0][SPD_DIMM_PART_NUM], + sizeof(uint8_t) * SPD_DIMM_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][118] << 8) | - (pei_data->spd_data[0][117] & 0xFF); + (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; @@ -446,14 +447,14 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = 1; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][122], - sizeof(uint8_t) * 4); + &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], + sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][128], - sizeof(uint8_t) * 18); + &pei_data->spd_data[0][SPD_DIMM_PART_NUM], + sizeof(uint8_t) * SPD_DIMM_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][118] << 8) | - (pei_data->spd_data[0][117] & 0xFF); + (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; |