diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_mrc.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 4027708617..8b5619cfb3 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -5,6 +5,7 @@ #include <cf9_reset.h> #include <string.h> #include <device/device.h> +#include <device/dram/ddr3.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cbmem.h> @@ -422,14 +423,14 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = 0; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][122], - sizeof(uint8_t) * 4); + &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], + sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][128], - sizeof(uint8_t) * 18); + &pei_data->spd_data[0][SPD_DIMM_PART_NUM], + sizeof(uint8_t) * SPD_DIMM_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][118] << 8) | - (pei_data->spd_data[0][117] & 0xFF); + (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; @@ -446,14 +447,14 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = 1; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][122], - sizeof(uint8_t) * 4); + &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], + sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][128], - sizeof(uint8_t) * 18); + &pei_data->spd_data[0][SPD_DIMM_PART_NUM], + sizeof(uint8_t) * SPD_DIMM_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][118] << 8) | - (pei_data->spd_data[0][117] & 0xFF); + (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; |