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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 22:08:18 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-07 12:59:28 +0100 |
| commit | 6f66f414a0907f79abf492cd9eca839c0849c7f6 (patch) | |
| tree | 3e74145128261014798af58111db31d616fd43dd /src/northbridge/via | |
| parent | 891b6c4d199418a08ba88e42d6c8945ce05205f1 (diff) | |
PCI ops: MMCONF_SUPPORT_DEFAULT is required
Doing PCI config operations via MMIO window by default is a
requirement, if supported by the platform. This means chipset
or CPU code must enable MMCONF operations early in bootblock
already, or before platform-specific romstage entry.
Platforms are allowed to have NO_MMCONF_SUPPORT only in the
case it is actually not implemented in the silicon.
Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/via')
| -rw-r--r-- | src/northbridge/via/vx900/early_vx900.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index eb5c79c9f9..6e1bc23cae 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -40,14 +40,13 @@ void vx900_enable_pci_config_space(void) * accessed */ pci_io_write_config8(HOST_CTR, 0x4f, 0x01); -#if CONFIG_MMCONF_SUPPORT /* COOL, now enable MMCONF */ u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); reg8 |= 3; pci_io_write_config8(TRAF_CTR, 0x60, reg8); + reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; pci_io_write_config8(TRAF_CTR, 0x61, reg8); -#endif } /** |