From 6f66f414a0907f79abf492cd9eca839c0849c7f6 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 1 Dec 2016 22:08:18 +0200 Subject: PCI ops: MMCONF_SUPPORT_DEFAULT is required MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/via/vx900/early_vx900.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/northbridge/via') diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index eb5c79c9f9..6e1bc23cae 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -40,14 +40,13 @@ void vx900_enable_pci_config_space(void) * accessed */ pci_io_write_config8(HOST_CTR, 0x4f, 0x01); -#if CONFIG_MMCONF_SUPPORT /* COOL, now enable MMCONF */ u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); reg8 |= 3; pci_io_write_config8(TRAF_CTR, 0x60, reg8); + reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; pci_io_write_config8(TRAF_CTR, 0x61, reg8); -#endif } /** -- cgit v1.2.3