diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-02 11:56:39 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-04 19:15:55 +0200 |
| commit | 7db506c3dd70f9ac0e8cdc481a47fa3835538be2 (patch) | |
| tree | 954275c199955bdee8b7b0d08aaba698e230f34e /src/northbridge/via/vx900 | |
| parent | fb190ed764450208c393a43da4ab15b0f9ccbe58 (diff) | |
src/northbridge: Remove unnecessary whitespace
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/via/vx900')
| -rw-r--r-- | src/northbridge/via/vx900/pcie.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/raminit_ddr3.c | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c index f717384e8f..ae81739185 100644 --- a/src/northbridge/via/vx900/pcie.c +++ b/src/northbridge/via/vx900/pcie.c @@ -52,7 +52,7 @@ static void vx900_pcie_link_init(device_t dev) /* Step 2: Wait for device to enter L0 state */ /* FIXME: implement timeout detection */ - while (0x8a != pci_read_config8(dev, 0x1c3)) ; + while (0x8a != pci_read_config8(dev, 0x1c3)); /* Step 3: Clear PCIe error status, then check for failures */ pci_write_config32(dev, 0x104, 0xffffffff); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index f4b61de88b..aff62f2773 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -737,7 +737,7 @@ static void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, printram("Hw MRS set is 0x%4x\n", reg16); pci_write_config16(MCU, 0xcc, reg16); /* Wait for MRS commands to be sent */ - while (pci_read_config8(MCU, 0xcc) & 1) ; + while (pci_read_config8(MCU, 0xcc) & 1); } /* @@ -1114,7 +1114,7 @@ static void vx900_rx_capture_range_calib(u8 pinswap) pci_write_config8(MCU, 0x71, reg8); /* Wait for it */ - while (pci_read_config8(MCU, 0x71) & 0x10) ; + while (pci_read_config8(MCU, 0x71) & 0x10); vx900_dram_exit_read_leveling(pinswap); } @@ -1146,7 +1146,7 @@ static void vx900_rx_dqs_delay_calib(u8 pinswap) pci_mod_config8(MCU, 0x71, 0x03, 0x02); /* Wait for calibration to complete */ - while (pci_read_config8(MCU, 0x71) & 0x02) ; + while (pci_read_config8(MCU, 0x71) & 0x02); vx900_dram_exit_read_leveling(pinswap); /* Restore the refresh counter */ @@ -1163,7 +1163,7 @@ static void vx900_tx_dqs_trigger_calib(u8 pattern) /* Trigger calibration */ pci_mod_config8(MCU, 0x75, 0, 0x20); /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x20) ; + while (pci_read_config8(MCU, 0x75) & 0x20); } /* @@ -1192,7 +1192,7 @@ static void vx900_tx_dq_delay_calib(void) /* Trigger calibration */ pci_mod_config8(MCU, 0x75, 0, 0x02); /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x02) ; + while (pci_read_config8(MCU, 0x75) & 0x02); } static void vx900_rxdqs_adjust(delay_range * dly) |