diff options
38 files changed, 106 insertions, 106 deletions
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index ec17b13b33..2c9f3aae28 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -102,7 +102,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 256; index++) { if ((sysconf.conf_io_addrx[index+4] == 0)) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; } @@ -118,7 +118,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; } @@ -136,7 +136,7 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, val = (nodeid & 0x3f); // 6 bits used sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + val = 3 | ((linkn & 0x7)<<4); // 8 bits used sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit if (sysconf.io_addr_num<(index+1)) @@ -150,9 +150,9 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, /* io range allocation */ index = (reg-0x80)>>3; - val = (nodeid & 0x3f) ; // 6 bits used + val = (nodeid & 0x3f); // 6 bits used sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + val = 3 | ((linkn & 0x7)<<4); // 8 bits used sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit if (sysconf.mmio_addr_num<(index+1)) @@ -478,7 +478,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes); // [39:8] store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; @@ -759,7 +759,7 @@ static void amdfam10_domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; sizek = limitk - basek; /* see if we need a hole from 0xa0000 to 0xbffff */ diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 3c91d2d97d..64d904f8e8 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -89,7 +89,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; } @@ -105,7 +105,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; } diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 28c16fb992..dda6bf96cb 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -89,7 +89,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; } @@ -105,7 +105,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; } diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 812935e108..36814638a9 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -106,7 +106,7 @@ static void enumerate_ht_chain(void) } real_last_unitid = next_unitid; real_last_pos = pos; - ht_dev_num++ ; + ht_dev_num++; #endif #if !CONFIG_HT_CHAIN_END_UNITID_BASE if (!next_unitid) diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 226d9a8c0a..9259147625 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -129,7 +129,7 @@ u32 get_io_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; } @@ -144,7 +144,7 @@ u32 get_mmio_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; } @@ -164,7 +164,7 @@ void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, val = (nodeid & 0x3f); // 6 bits used sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + val = 3 | ((linkn & 0x7)<<4); // 8 bits used sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit if (sysconf.io_addr_num < (index+1)) @@ -180,9 +180,9 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, /* io range allocation */ index = (reg-0x80)>>3; - val = (nodeid & 0x3f) ; // 6 bits used + val = (nodeid & 0x3f); // 6 bits used sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + val = 3 | ((linkn & 0x7)<<4); // 8 bits used sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit if (sysconf.mmio_addr_num<(index+1)) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 354e70316f..40f57046e8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -577,7 +577,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes); // [39:8] store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; @@ -966,7 +966,7 @@ static void amdfam10_domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; sizek = limitk - basek; /* see if we need a hole from 0xa0000 to 0xbffff */ diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 7ddf93f120..0e64397ff0 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -108,7 +108,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b u32 val; // put node and link in correct bit - val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8) ; + val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8); for (reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; @@ -131,7 +131,7 @@ u32 get_sblk(void) u32 reg; /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64); - return ((reg>>8) & 3) ; + return ((reg>>8) & 3); } diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index b4838b44d5..2baf886c31 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1541,7 +1541,7 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) pDat->PortList[i+1].CompositeFrequencyCap = temp; ASSERT (temp != 0); - for (j = 19; ; j--) + for (j = 19;; j--) { if ((j == 16) || (j == 15)) continue; @@ -1691,7 +1691,7 @@ static void hammerSublinkFixup(sMainData *pDat) pDat->PortList[hiIndex].CompositeFrequencyCap = temp; pDat->PortList[hiIndex+1].CompositeFrequencyCap = temp; - for (k = 19; ; k--) + for (k = 19;; k--) { if ((j == 16) || (j == 15)) continue; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 169b4b3369..4c68f41337 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -73,7 +73,7 @@ static u32 get_nodes(void) u32 nodes; dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ; + nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); #if CONFIG_MAX_PHYSICAL_CPUS > 8 nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); #endif diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 887a23b1f0..ef4b829397 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -1572,7 +1572,7 @@ static unsigned verify_dualcore(unsigned nodes) totalcpus = 0; for (node = 0; node < nodes; node++) { - tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ; + tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3; totalcpus += (tmp + 1); } diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 9fa0034848..48a4709f74 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -435,7 +435,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 out: #endif -end_of_chain: ; +end_of_chain:; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (offset_unitid && (ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { @@ -663,7 +663,7 @@ static int ht_setup_chains(uint8_t ht_c_num) regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n;it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16; - dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos) ; + dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos); dword &= ~(0xffff<<8); dword |= (reg & 0xffff0000)>>8; pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword); diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 4ef621c96d..a42614e3cd 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1607,7 +1607,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) { const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { + for (param = &speed[0]; param->cycle_time; param++) { if (min_cycle_time > (param+1)->cycle_time) { break; } diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 2d05951513..0cea94a0a2 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -479,7 +479,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st uint8_t *buf_a, *buf_b; uint32_t ecc_bit; uint32_t dword; - uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8] ; //8 node, channel 2, receiver 8 + uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8]; //8 node, channel 2, receiver 8 int i; diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index cfc5dda718..53f24339a3 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -77,7 +77,7 @@ static inline unsigned get_sblk(void) u32 reg; /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - return ((reg>>8) & 3) ; + return ((reg>>8) & 3); } static inline unsigned get_sbbusn(unsigned sblk) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 87863b143e..d3ae2a3cf4 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1700,7 +1700,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (!(pDCTstat->DIMMValid & (1 << val))) /*disable memclk*/ DramTimingLo |= 1 << (dword+24); - dword++ ; + dword++; } } } @@ -3629,7 +3629,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, p = (u8 *) pDCTstat; start = 0; stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop ; i++) { + for (i = start; i < stop; i++) { p[i] = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index da2a4fe0c6..bd26a6fc45 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -226,7 +226,7 @@ static const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2}; CS3 M[B,A]_CLK_H/L[5] Then: - ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 + ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 MEMCLK_MAPPING EQU 00010000b, 00000100b, 00001000b, 00100000b, 00000000b, 00000000b, 00000000b, 00000000b */ @@ -5258,7 +5258,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, val = p[dword]; byte &= ~val; } - dword++ ; + dword++; } DramTimingLo &= ~(0xff << 24); DramTimingLo |= byte << 24; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c index 5030562c7c..3c15e3f845 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c @@ -16,7 +16,7 @@ static void AmdMemPCIRead(SBDFO loc, u32 *Value) { /* Convert SBDFO into a CF8 Address */ - loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16) ; + loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16); loc |= 0x80000000; outl(loc, 0xCF8); @@ -27,7 +27,7 @@ static void AmdMemPCIRead(SBDFO loc, u32 *Value) static void AmdMemPCIWrite(SBDFO loc, u32 *Value) { /* Convert SBDFO into a CF8 Address */ - loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16) ; + loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16); loc |= 0x80000000; outl(loc, 0xCF8); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index a40a628187..4b6090f1e5 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -402,7 +402,7 @@ static void pci_domain_enable(device_t dev) // print_conf(); - do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) + do_vsmbios(); // do the magic stuff here, so prepare your tambourine;) // print_conf(); diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 395d9253a9..3be0248571 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -672,8 +672,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) /* 2us delay (200 clocks @ 200MHz). We probably really don't need this but.... better safe. */ /* Wait 2 PORT61 ticks. between 15us and 30us */ /* This would be endless if the timer is stuck. */ - while ((inb(0x61))) ; /* find the first edge */ - while (!(~inb(0x61))) ; + while ((inb(0x61))); /* find the first edge */ + while (!(~inb(0x61))); /* Force Precharge All on the next command, auto-refresh */ msrnum = MC_CFCLK_DBUG; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 6769d111b0..fb115ff7b2 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -377,7 +377,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] } resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof(buf), " <node %x link %x>", @@ -795,7 +795,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 1ca0df98e4..c44641965a 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -370,7 +370,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] } resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof(buf), " <node %x link %x>", @@ -802,7 +802,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 334cdb215c..c87d68abb7 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -391,7 +391,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] } resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof(buf), " <node %x link %x>", @@ -824,7 +824,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; sizek = limitk - basek; diff --git a/src/northbridge/intel/fsp_sandybridge/report_platform.c b/src/northbridge/intel/fsp_sandybridge/report_platform.c index 60a3e00e4f..39bbc09510 100644 --- a/src/northbridge/intel/fsp_sandybridge/report_platform.c +++ b/src/northbridge/intel/fsp_sandybridge/report_platform.c @@ -41,7 +41,7 @@ static void report_cpu_info(void) strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx; diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 3f56b94945..47203b4186 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -49,12 +49,12 @@ static void init_egress(void) EPBAR32(0x11c) = 0x00005555; EPBAR32(0x20) |= 1 << 16; - while ((EPBAR8(0x26) & 1) != 0) ; + while ((EPBAR8(0x26) & 1) != 0); /* VC1: enable */ EPBAR32(0x20) |= 1 << 31; - while ((EPBAR8(0x26) & 2) != 0) ; + while ((EPBAR8(0x26) & 2) != 0); } /* MCH side */ @@ -72,7 +72,7 @@ static void init_dmi(int b2step) /* VC1: enable */ DMIBAR32(0x20) |= 1 << 31; - while ((DMIBAR8(0x26) & 2) != 0) ; + while ((DMIBAR8(0x26) & 2) != 0); /* additional configuration. */ DMIBAR32(0x200) |= 3 << 13; diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 711ff48d69..aed125c8bc 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -36,7 +36,7 @@ static void report_cpu_info(void) strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx; diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index fa00df8eea..4804544555 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -85,7 +85,7 @@ void dump_spd_registers(void) int i; printk(BIOS_DEBUG, "\ndimm %02x", device); - for (i = 0; (i < 256) ; i++) { + for (i = 0; (i < 256); i++) { if ((i % 16) == 0) { printk(BIOS_DEBUG, "\n%02x: ", i); } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dda41bd6d7..4373167693 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -285,7 +285,7 @@ static void i945_setup_egress_port(void) printk(BIOS_DEBUG, "Loading port arbitration table ..."); /* Loop until bit 0 becomes 0 */ timeout = 0x7fffff; - while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ; + while ((EPBAR16(EPVC1RSTS) & 1) && --timeout); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else @@ -297,7 +297,7 @@ static void i945_setup_egress_port(void) printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ timeout = 0x7fff; - while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ; + while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else @@ -390,7 +390,7 @@ static void i945_setup_dmi_rcrb(void) printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ timeout = 0x7ffff; - while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ; + while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else @@ -490,7 +490,7 @@ static void i945_setup_dmi_rcrb(void) /* wait for bit toggle to 0 */ printk(BIOS_DEBUG, "Waiting for DMI hardware..."); timeout = 0x7fffff; - while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ; + while ((DMIBAR8(0x32) & (1 << 1)) && --timeout); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else @@ -593,7 +593,7 @@ static void i945_setup_pci_express_x16(void) /* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout); reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -618,7 +618,7 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout); reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -793,7 +793,7 @@ disable_pciexpress_x16_link: printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); - (reg32 & 0x000f0000) && --timeout;) ; + (reg32 & 0x000f0000) && --timeout;); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 69e7108271..d9159966dc 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -173,12 +173,12 @@ static void read128(u32 addr, u64 * out) static void write_1d0(u32 val, u16 addr, int bits, int flag) { write_mchbar32(0x1d0, 0); - while (read_mchbar32(0x1d0) & 0x800000) ; + while (read_mchbar32(0x1d0) & 0x800000); write_mchbar32(0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); write_mchbar32(0x1d0, 0x40000000 | addr); - while (read_mchbar32(0x1d0) & 0x800000) ; + while (read_mchbar32(0x1d0) & 0x800000); } /* OK */ @@ -186,11 +186,11 @@ static u16 read_1d0(u16 addr, int split) { u32 val; write_mchbar32(0x1d0, 0); - while (read_mchbar32(0x1d0) & 0x800000) ; + while (read_mchbar32(0x1d0) & 0x800000); write_mchbar32(0x1d0, 0x80000000 | (((read_mchbar8(0x246) >> 2) & 3) + 0x361 - addr)); - while (read_mchbar32(0x1d0) & 0x800000) ; + while (read_mchbar32(0x1d0) & 0x800000); val = read_mchbar32(0x1d8); write_1d0(0, 0x33d, 0, 0); write_1d0(0, 0x33d, 0, 0); @@ -289,12 +289,12 @@ read_500(struct raminfo *info, int channel, u16 addr, int split) u32 val; info->last_500_command[channel] = 0x80000000; write_mchbar32(0x500 + (channel << 10), 0); - while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000); write_mchbar32(0x500 + (channel << 10), 0x80000000 | (((read_mchbar8(0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr)); - while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000); val = read_mchbar32(0x508 + (channel << 10)); return val & ((1 << split) - 1); } @@ -309,12 +309,12 @@ write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, write_500(info, channel, 0, 0xb61, 0, 0); } write_mchbar32(0x500 + (channel << 10), 0); - while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000); write_mchbar32(0x504 + (channel << 10), (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); write_mchbar32(0x500 + (channel << 10), 0x40000000 | addr); - while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000); } static int rw_test(int rank) @@ -391,7 +391,7 @@ static u32 get_580(int channel, u8 addr) write_mchbar32(0x580 + (channel << 10), 0x8493c012 | addr); write_mchbar8(0x580 + (channel << 10), read_mchbar8(0x580 + (channel << 10)) | 1); - while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000)) ; + while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000)); write_mchbar8(0x580 + (channel << 10), read_mchbar8(0x580 + (channel << 10)) & ~1); return ret; @@ -548,7 +548,7 @@ static void set_334(int zero) } write_mchbar32(0x130, read_mchbar32(0x130) | 1); /* OK */ - while (read_mchbar8(0x130) & 1) ; /* OK */ + while (read_mchbar8(0x130) & 1); /* OK */ } static void rmw_1d0(u16 addr, u32 and, u32 or, int split, int flag) @@ -1593,7 +1593,7 @@ static void collect_system_info(struct raminfo *info) unsigned channel; /* Wait for some bit, maybe TXT clear. */ - while (!(read8((u8 *)0xfed40000) & (1 << 7))) ; + while (!(read8((u8 *)0xfed40000) & (1 << 7))); if (!info->heci_bar) gav(info->heci_bar = @@ -1756,7 +1756,7 @@ static const struct ram_training *get_cached_training(void) /* FIXME: add timeout. */ static void wait_heci_ready(void) { - while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ; // = 0x8000000c + while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)); // = 0x8000000c write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); } @@ -1769,7 +1769,7 @@ static void wait_heci_cb_avail(int len) u32 raw; } csr; - while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ; + while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)); do csr.raw = read32(DEFAULT_HECIBAR + 0x4); @@ -1971,7 +1971,7 @@ static void setup_heci_uma(struct raminfo *info) write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK while (read16(DEFAULT_RCBA + 0x46) & 2 - && read16(DEFAULT_DMIBAR + 0x3e) & 2) ; + && read16(DEFAULT_DMIBAR + 0x3e) & 2); } write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb); @@ -4551,7 +4551,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar8(0x5f4, 0x1); /* OK */ write_mchbar32(0x130, read_mchbar32(0x130) & 0xfffffffd); // | 2 when ? - while (read_mchbar32(0x130) & 1) ; + while (read_mchbar32(0x130) & 1); gav(read_1d0(0x14b, 7)); // = 0x81023100 write_1d0(0x30, 0x14b, 7, 1); read_1d0(0xd6, 6); // = 0xfa008080 // !!!! @@ -4622,7 +4622,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) [0][0] [0] << 29)); - while (read_mchbar8(0x130) & 1) ; // !!!! + while (read_mchbar8(0x130) & 1); // !!!! read_1d0(0xa1, 6); // = 0x1cf4054 // !!!! read_1d0(0x2f3, 6); // = 0x10a4054 // !!!! read_1d0(0x21c, 6); // = 0xafa00c0 // !!!! @@ -4962,7 +4962,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) udelay(1000); #endif u16 ecx; - for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--) ; // OK + for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--); // OK write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1e46263f93..46dc7c7843 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -225,7 +225,7 @@ static void wait_txt_clear(void) if (!(read32((void *)0xfed30010) & 1)) return; /* Wait for TXT clear. */ - while (!(read8((void *)0xfed40000) & (1 << 7))) ; + while (!(read8((void *)0xfed40000) & (1 << 7))); } static void sfence(void) @@ -1322,7 +1322,7 @@ static void dram_jedecreset(ramctr_timing * ctrl) u32 reg, addr; int channel; - while (!(MCHBAR32(0x5084) & 0x10000)) ; + while (!(MCHBAR32(0x5084) & 0x10000)); do { reg = MCHBAR32(0x428c); } while ((reg & 0x14) == 0); @@ -3997,7 +3997,7 @@ static void restore_timings(ramctr_timing * ctrl) u32 reg, addr; - while (!(MCHBAR32(0x5084) & 0x10000)) ; + while (!(MCHBAR32(0x5084) & 0x10000)); do { reg = MCHBAR32(0x428c); } while ((reg & 0x14) == 0); diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 39bff65b8b..d137e8b63b 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -34,7 +34,7 @@ static void report_cpu_info(void) strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx; diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index 7eb67ff071..f03869e346 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -80,13 +80,13 @@ static void init_egress(void) EPBAR32(0x20) = reg32; /* Wait for table load */ - while ((EPBAR8(0x26) & (1 << 0)) != 0) ; + while ((EPBAR8(0x26) & (1 << 0)) != 0); /* VC1: enable */ EPBAR32(0x20) |= 1 << 31; /* Wait for VC1 */ - while ((EPBAR8(0x26) & (1 << 1)) != 0) ; + while ((EPBAR8(0x26) & (1 << 1)) != 0); printk(BIOS_DEBUG, "Done Egress Port\n"); } diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 14a17d4771..aad851d929 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -303,8 +303,8 @@ static const u8 Init_Rank_Reg_Table[] = { static const u16 DDR2_MRS_table[] = { /* CL: 2, 3, 4, 5 */ - 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4 ;Use 1X-bandwidth MA table to init DRAM */ - 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8 ;Use 1X-bandwidth MA table to init DRAM */ + 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4; Use 1X-bandwidth MA table to init DRAM */ + 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8; Use 1X-bandwidth MA table to init DRAM */ }; #define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 7cd557a02c..7ac5fe1999 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -325,7 +325,7 @@ static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm // { DLL: reset. A11(MA8)=1 } // // DDR2 CL = 2 CL = 3 CL = 4 CL = 5 CL = 6(Burst type = interleave)(WR fine tune in code) -static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM +static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHA_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -534,7 +534,7 @@ static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; / // { DLL: reset. A11(MA8)=1 } // // DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) -static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM +static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index b9466b9813..0c5f63c2d4 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -304,7 +304,7 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E3T, Rx55E3T}, // 200/200 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E1T, Rx55E1T}, // 200/266 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T} // 200/333 -// DDR2 Both E3T and E2T Fail, need set to E1T, db PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 00110011b, 00000000b, Rx54E3T, Rx55E3T ;200/266 +// DDR2 Both E3T and E2T Fail, need set to E1T, db PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 00110011b, 00000000b, Rx54E3T, Rx55E3T; 200/266 }, // cpu166 { @@ -326,7 +326,7 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu333 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100; DO NOT Support {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 333/133 {PH3_3_3_3, PH0_0_0_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E0T, Rx55E0T}, // 333/166 {PH2_3_3_2, PH0_0_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E1T, Rx55E1T}, // 333/200 @@ -348,7 +348,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = {PH1_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x06, 0x00, Rx54E3T, Rx55E3T}, // 100/133 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/166 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/200 - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // ;100/266 + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/266 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T} // 100/333 }, // cpu133 @@ -380,7 +380,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu266 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 266/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 266/100; DO NOT Support {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 266/133 {PH2_2_1_2, PH0_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E0T, Rx55E0T}, // 266/166 {PH3_3_3_3, PH0_0_3_3, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E2T, Rx55E2T}, // 266/200 @@ -389,7 +389,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu333 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100; DO NOT Support {PH3_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 333/133 {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54L1T, Rx55L1T}, // 333/166 {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E1T, Rx55E1T}, // 333/200 @@ -568,7 +568,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) } } - /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4 ; =1 BL = 8 */ + /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4; =1 BL = 8 */ if (BL & 0x08) /*All Assembly support BL = 8 */ BL = 0x8; /*set bit3 */ diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index 08299c7a94..e9190fac30 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -16,14 +16,14 @@ #ifndef DRIVINGCLKPHASEDATA_H #define DRIVINGCLKPHASEDATA_H -//extern u8 DDR2_DQSA_Driving_Table[4] ; -//extern u8 DDR2_DQSB_Driving_Table[2] ; +//extern u8 DDR2_DQSA_Driving_Table[4]; +//extern u8 DDR2_DQSB_Driving_Table[2]; -//extern u8 DDR2_DQA_Driving_Table[4] ; -//extern u8 DDR2_DQB_Driving_Table[2] ; +//extern u8 DDR2_DQA_Driving_Table[4]; +//extern u8 DDR2_DQB_Driving_Table[2]; -//extern u8 DDR2_CSA_Driving_Table_x8[4] ; -//extern u8 DDR2_CSB_Driving_Table_x8[2] ; +//extern u8 DDR2_CSA_Driving_Table_x8[4]; +//extern u8 DDR2_CSB_Driving_Table_x8[2]; //extern u8 DDR2_CSA_Driving_Table_x16[4]; //extern u8 DDR2_CSB_Driving_Table_x16[2]; @@ -31,7 +31,7 @@ //extern u8 DDR2_MAA_Driving_Table[MA_Table][4]; //extern u8 DDR2_MAB_Driving_Table[MA_Table][2]; -//extern u8 DDR2_DCLKA_Driving_Table[4] ; +//extern u8 DDR2_DCLKA_Driving_Table[4]; //extern u8 DDR2_DCLKB_Driving_Table[4]; #define DUTY_CYCLE_FREQ_NUM 6 diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 6e11704e28..6592efdefd 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -135,7 +135,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) } if (!AllDimmSupportedCL) { /*if equal 0, no supported CL */ PRINT_DEBUG_MEM("SPD Data Error, Can not get CL !!!! \r"); - for (;;) ; + for (;;); } /*Get CL Value */ @@ -192,7 +192,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) if (CycTime <= 0) { //error! - for (;;) ; + for (;;); } /* cycle time value diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c index f717384e8f..ae81739185 100644 --- a/src/northbridge/via/vx900/pcie.c +++ b/src/northbridge/via/vx900/pcie.c @@ -52,7 +52,7 @@ static void vx900_pcie_link_init(device_t dev) /* Step 2: Wait for device to enter L0 state */ /* FIXME: implement timeout detection */ - while (0x8a != pci_read_config8(dev, 0x1c3)) ; + while (0x8a != pci_read_config8(dev, 0x1c3)); /* Step 3: Clear PCIe error status, then check for failures */ pci_write_config32(dev, 0x104, 0xffffffff); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index f4b61de88b..aff62f2773 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -737,7 +737,7 @@ static void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, printram("Hw MRS set is 0x%4x\n", reg16); pci_write_config16(MCU, 0xcc, reg16); /* Wait for MRS commands to be sent */ - while (pci_read_config8(MCU, 0xcc) & 1) ; + while (pci_read_config8(MCU, 0xcc) & 1); } /* @@ -1114,7 +1114,7 @@ static void vx900_rx_capture_range_calib(u8 pinswap) pci_write_config8(MCU, 0x71, reg8); /* Wait for it */ - while (pci_read_config8(MCU, 0x71) & 0x10) ; + while (pci_read_config8(MCU, 0x71) & 0x10); vx900_dram_exit_read_leveling(pinswap); } @@ -1146,7 +1146,7 @@ static void vx900_rx_dqs_delay_calib(u8 pinswap) pci_mod_config8(MCU, 0x71, 0x03, 0x02); /* Wait for calibration to complete */ - while (pci_read_config8(MCU, 0x71) & 0x02) ; + while (pci_read_config8(MCU, 0x71) & 0x02); vx900_dram_exit_read_leveling(pinswap); /* Restore the refresh counter */ @@ -1163,7 +1163,7 @@ static void vx900_tx_dqs_trigger_calib(u8 pattern) /* Trigger calibration */ pci_mod_config8(MCU, 0x75, 0, 0x20); /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x20) ; + while (pci_read_config8(MCU, 0x75) & 0x20); } /* @@ -1192,7 +1192,7 @@ static void vx900_tx_dq_delay_calib(void) /* Trigger calibration */ pci_mod_config8(MCU, 0x75, 0, 0x02); /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x02) ; + while (pci_read_config8(MCU, 0x75) & 0x02); } static void vx900_rxdqs_adjust(delay_range * dly) |