diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-02 11:56:39 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-04 19:15:55 +0200 |
| commit | 7db506c3dd70f9ac0e8cdc481a47fa3835538be2 (patch) | |
| tree | 954275c199955bdee8b7b0d08aaba698e230f34e /src/northbridge/via/cx700 | |
| parent | fb190ed764450208c393a43da4ab15b0f9ccbe58 (diff) | |
src/northbridge: Remove unnecessary whitespace
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/via/cx700')
| -rw-r--r-- | src/northbridge/via/cx700/raminit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 14a17d4771..aad851d929 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -303,8 +303,8 @@ static const u8 Init_Rank_Reg_Table[] = { static const u16 DDR2_MRS_table[] = { /* CL: 2, 3, 4, 5 */ - 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4 ;Use 1X-bandwidth MA table to init DRAM */ - 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8 ;Use 1X-bandwidth MA table to init DRAM */ + 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4; Use 1X-bandwidth MA table to init DRAM */ + 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8; Use 1X-bandwidth MA table to init DRAM */ }; #define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) |