Uniformly spell frequency unit symbol as Hz

Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

7 files changed, 22 insertions, 22 deletions

diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index f42bef2db0..2247a256af 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -1276,7 +1276,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
 
 	/* Trd */
 
-	/* Set to a 7 clock read delay. This is for 133Mhz
+	/* Set to a 7 clock read delay. This is for 133MHz
 	 *  with a CAS latency of 2.5  if 2.0 a 6 clock
 	 *  delay is good  */
 
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index e5920df0bd..909e740131 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -1132,7 +1132,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
 
 	/* Trd */
 
-	/* Set to a 7 clock read delay. This is for 133Mhz
+	/* Set to a 7 clock read delay. This is for 133MHz
 	 *  with a CAS latency of 2.5  if 2.0 a 6 clock
 	 *  delay is good  */
 
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 55be449636..1e335f5f13 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -439,12 +439,12 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs say use 55 for all 200Mhz */
+		/* Docs say use 55 for all 200MHz */
 		drt |= (0x055<<24);
 	}
-	else if(value <= 0x60) { /* 167 Mhz */
+	else if(value <= 0x60) { /* 167 MHz */
 		/* according to new documentation CAS latency is 00
-		 * for bits 3:2 for all 167 Mhz
+		 * for bits 3:2 for all 167 MHz
 		drt |= ((index&3)<<2); */  /* set CAS latency */
 		if((index&0x0ff00)<=0x03000) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
@@ -484,10 +484,10 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs state to use 99 for all 167 Mhz */
+		/* Docs state to use 99 for all 167 MHz */
 		drt |= (0x099<<24);
 	}
-	else if(value <= 0x75) { /* 133 Mhz */
+	else if(value <= 0x75) { /* 133 MHz */
 		drt |= ((index&3)<<2);  /* set CAS latency */
 		if((index&0x0ff00)<=0x03c00) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 11f26ee30b..0e6e204832 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -445,12 +445,12 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs say use 55 for all 200Mhz */
+		/* Docs say use 55 for all 200MHz */
 		drt |= (0x055<<24);
 	}
-	else if(value <= 0x60) { /* 167 Mhz */
+	else if(value <= 0x60) { /* 167 MHz */
 		/* according to new documentation CAS latency is 00
-		 * for bits 3:2 for all 167 Mhz
+		 * for bits 3:2 for all 167 MHz
 		drt |= ((index&3)<<2); */  /* set CAS latency */
 		if((index&0x0ff00)<=0x03000) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
@@ -490,10 +490,10 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs state to use 99 for all 167 Mhz */
+		/* Docs state to use 99 for all 167 MHz */
 		drt |= (0x099<<24);
 	}
-	else if(value <= 0x75) { /* 133 Mhz */
+	else if(value <= 0x75) { /* 133 MHz */
 		drt |= ((index&3)<<2);  /* set CAS latency */
 		if((index&0x0ff00)<=0x03c00) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 443972e4d6..4f5a989dc6 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -433,12 +433,12 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs say use 55 for all 200Mhz */
+		/* Docs say use 55 for all 200MHz */
 		drt |= (0x055<<24);
 	}
-	else if(value <= 0x60) { /* 167 Mhz */
+	else if(value <= 0x60) { /* 167 MHz */
 		/* according to new documentation CAS latency is 00
-		 * for bits 3:2 for all 167 Mhz
+		 * for bits 3:2 for all 167 MHz
 		drt |= ((index&3)<<2); */  /* set CAS latency */
 		if((index&0x0ff00)<=0x03000) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
@@ -478,10 +478,10 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs state to use 99 for all 167 Mhz */
+		/* Docs state to use 99 for all 167 MHz */
 		drt |= (0x099<<24);
 	}
-	else if(value <= 0x75) { /* 133 Mhz */
+	else if(value <= 0x75) { /* 133 MHz */
 		drt |= ((index&3)<<2);  /* set CAS latency */
 		if((index&0x0ff00)<=0x03c00) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 26c0c4bcb5..7d283a1941 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -416,7 +416,7 @@ static void sdram_enable(void)
 	/* 0. Wait until power/voltages and clocks are stable (200us). */
 	udelay(200);
 
-	/* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 Mhz). */
+	/* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 MHz). */
 	PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
 	do_ram_command(RAM_COMMAND_NOP);
 	udelay(200);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 42233e82db..e823bab455 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2028,10 +2028,10 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 
 	printk(BIOS_DEBUG, "Render: ");
 	switch (freq) {
-	case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
-	case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
-	case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
-	case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
+	case CRCLK_166MHz: printk(BIOS_DEBUG, "166MHz"); break;
+	case CRCLK_200MHz: printk(BIOS_DEBUG, "200MHz"); break;
+	case CRCLK_250MHz: printk(BIOS_DEBUG, "250MHz"); break;
+	case CRCLK_400MHz: printk(BIOS_DEBUG, "400MHz"); break;
 	}
 
 	if (i945_silicon_revision() == 0) {