diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 19:01:28 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-16 12:06:53 +0000 |
| commit | 71902014e33d641ac2481a7e1f7670fee6a78a25 (patch) | |
| tree | 6fb445a5e7a603a3451b04b957a8c3a7ed69de90 /src/northbridge/intel/sandybridge/raminit_common.c | |
| parent | 2f3cc0035dd29c0d63aa8a32876c84256304b210 (diff) | |
nb/intel/sandybridge: Drop write_controller_mr() function
The only reason to write the MR values to the training result registers
is for EV (Electrical Validation) usage. The hardware doesn't need it.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I808174494729453f4ebcaa13258d735faae68d72
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 60a218b419..3fd8cb0b3d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -4078,18 +4078,6 @@ void normalize_training(ramctr_timing *ctrl) } } -void write_controller_mr(ramctr_timing *ctrl) -{ - int channel, slotrank; - - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = - make_mr0(ctrl, slotrank); - MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = - make_mr1(ctrl, slotrank, channel); - } -} - int channel_test(ramctr_timing *ctrl) { int channel, slotrank, lane; |