nb/intel/sandybridge: Reduce the scope of get_CWL()

It is only used once, and can thus be moved to the same file.

Change-Id: I4ee0621449da7fa1970a475d5a2f6e66546357ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 0 insertions, 35 deletions

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 3ab8df2403..60a218b419 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -80,41 +80,6 @@ static u32 get_XOVER_CMD(u8 rankmap)
 	return reg;
 }
 
-/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */
-u8 get_CWL(u32 tCK)
-{
-	/* Get CWL based on tCK using the following rule */
-	switch (tCK) {
-	case TCK_1333MHZ:
-		return 12;
-
-	case TCK_1200MHZ:
-	case TCK_1100MHZ:
-		return 11;
-
-	case TCK_1066MHZ:
-	case TCK_1000MHZ:
-		return 10;
-
-	case TCK_933MHZ:
-	case TCK_900MHZ:
-		return 9;
-
-	case TCK_800MHZ:
-	case TCK_700MHZ:
-		return 8;
-
-	case TCK_666MHZ:
-		return 7;
-
-	case TCK_533MHZ:
-		return 6;
-
-	default:
-		return 5;
-	}
-}
-
 void dram_find_common_params(ramctr_timing *ctrl)
 {
 	size_t valid_dimms;