diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-02-24 19:21:33 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-28 15:28:19 +0000 |
| commit | f8daf86282c1be33643ace4e9f453e7548cab41c (patch) | |
| tree | 955ae7a9b9533b64b40ccc250a9f64b4630fedfc /src/northbridge/intel/sandybridge/acpi | |
| parent | ec97e0a29dc7441a191bc14179b36a8f233a8122 (diff) | |
nb/intel/sandybridge/acpi: Support setting PCI bars above 4G
Although coreboot can allocate resources above 4G, Linux does not
consider those allocation valid when there is no region above 4G in
_CRS and disables the device.
TESTED: x220 with and external GPU via the expresscard slot. Linux
does not touch the BARs allocated above 4G.
Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/acpi')
| -rw-r--r-- | src/northbridge/intel/sandybridge/acpi/hostbridge.asl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 5421725a68..fa472b1aa5 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -326,6 +326,12 @@ Name (MCRS, ResourceTemplate() 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,, PM01) + // PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM02) + // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, @@ -333,6 +339,9 @@ Name (MCRS, ResourceTemplate() 0x00005000,,, TPMR) }) +External (\A4GS, IntObj) +External (\A4GB, IntObj) + Method (_CRS, 0, Serialized) { // Find PCI resource area in MCRS @@ -359,5 +368,15 @@ Method (_CRS, 0, Serialized) PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 PLEN = PMAX - PMIN + 1 + If (A4GS != 0) { + CreateQwordField(MCRS, ^PM02._MIN, MMIN) + CreateQwordField(MCRS, ^PM02._MAX, MMAX) + CreateQwordField(MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + MLEN = \A4GS + MMIN = \A4GB + MMAX = MMIN + MLEN - 1 + } + Return (MCRS) } |