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author | Elyes Haouas <ehaouas@noos.fr> | 2022-03-07 17:30:02 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-28 14:14:27 +0000 |
commit | ec97e0a29dc7441a191bc14179b36a8f233a8122 (patch) | |
tree | 8bd73a80d8170e01fdc77dd4ec1e500b6c48ad03 /src/northbridge/intel/sandybridge/acpi | |
parent | e4cf3fa36df5e4b7e8907f29350141a2fcb88f37 (diff) |
include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values
Regarding JEDEC Standard No. 21-C, Release 30, page 13, DDR4_SPD_72B_SO_RDIMM
and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09.
There is no affected board in coreboot tree.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/acpi')
0 files changed, 0 insertions, 0 deletions