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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-11 16:06:19 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 12:02:01 +0000 |
commit | c6ff1ac29e9ecc3c62662f43b5ea260578fbb3d5 (patch) | |
tree | fb523afbc362d5285a4d6f7d292350a3a2a13a20 /src/northbridge/intel/pineview/pineview.h | |
parent | b31aee9973d1dcf9d1d7840a012c2b70367c4680 (diff) |
nb/intel/pineview: Move the boilerplate mainboard_romstage_entry
The mainboard_romstage_entry function is mostly boilerplate, so move
it to a common location and provide mainboard specific callbacks.
Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/pineview/pineview.h')
-rw-r--r-- | src/northbridge/intel/pineview/pineview.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 8c32e17113..65d21cfb8d 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -235,6 +235,11 @@ u32 decode_igd_memory_size(const u32 gms); u32 decode_igd_gtt_size(const u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); +/* Mainboard romstage callback functions */ +void mb_enable_lpc(void); +void get_mb_spd_addrmap(u8 *spd_addr_map); +void mb_pirq_setup(void); /* optional */ + struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); |