From c6ff1ac29e9ecc3c62662f43b5ea260578fbb3d5 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 11 Jan 2019 16:06:19 +0100 Subject: nb/intel/pineview: Move the boilerplate mainboard_romstage_entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mainboard_romstage_entry function is mostly boilerplate, so move it to a common location and provide mainboard specific callbacks. Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30851 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki --- src/northbridge/intel/pineview/pineview.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/northbridge/intel/pineview/pineview.h') diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 8c32e17113..65d21cfb8d 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -235,6 +235,11 @@ u32 decode_igd_memory_size(const u32 gms); u32 decode_igd_gtt_size(const u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); +/* Mainboard romstage callback functions */ +void mb_enable_lpc(void); +void get_mb_spd_addrmap(u8 *spd_addr_map); +void mb_pirq_setup(void); /* optional */ + struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); -- cgit v1.2.3