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authorAngel Pons <th3fanbus@gmail.com>2020-02-17 13:08:53 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 13:04:20 +0000
commit95de2317c6c6379e43d3b3c27d34eb66198dbe0a (patch)
treee0df0c7dfce199b95609be41f0d806b5829d8005 /src/northbridge/intel/nehalem/acpi/nehalem.asl
parent2aff3005e0ebdf99c0a0f063f023536f601a879b (diff)
nb/intel/nehalem: Rename to ironlake
The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/nehalem/acpi/nehalem.asl')
-rw-r--r--src/northbridge/intel/nehalem/acpi/nehalem.asl55
1 files changed, 0 insertions, 55 deletions
diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl
deleted file mode 100644
index 404801ec3f..0000000000
--- a/src/northbridge/intel/nehalem/acpi/nehalem.asl
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "../nehalem.h"
-#include "hostbridge.asl"
-#include <southbridge/intel/common/rcba.h>
-
-/* PCI Device Resource Consumption */
-Device (PDRC)
-{
- Name (_HID, EISAID("PNP0C02"))
- Name (_UID, 1)
-
- Name (PDRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
- Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
- Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
- Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
- Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
- Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
- Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
-
-#if CONFIG(CHROMEOS_RAMOOPS)
- Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
- CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
-#endif
-
- /* Required for SandyBridge sighting 3715511 */
- Memory32Fixed(ReadWrite, 0x20000000, 0x00200000)
- Memory32Fixed(ReadWrite, 0x40000000, 0x00200000)
- })
-
- // Current Resource Settings
- Method (_CRS, 0, Serialized)
- {
- Return(PDRS)
- }
-}
-
-// Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/pch.asl>