nb/intel/nehalem: Rename to ironlake

The code is for Arrandale CPUs, whose System Agent is Ironlake.

This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.

Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.

Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

19 files changed, 42 insertions, 42 deletions

diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index cfd7fe248d..512149bfee 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -13,7 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
-config NORTHBRIDGE_INTEL_NEHALEM
+config NORTHBRIDGE_INTEL_IRONLAKE
 	bool
 	select CPU_INTEL_MODEL_2065X
 	select VGA
@@ -22,7 +22,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
 	select CACHE_MRC_SETTINGS
 	select HAVE_DEBUG_RAM_SETUP
 
-if NORTHBRIDGE_INTEL_NEHALEM
+if NORTHBRIDGE_INTEL_IRONLAKE
 
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc
index 225f0ce812..1fde37d9f6 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/ironlake/Makefile.inc
@@ -13,7 +13,7 @@
 # GNU General Public License for more details.
 #
 
-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE),y)
 
 bootblock-y += bootblock.c
 
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/ironlake/acpi.c
index 43b13c286a..198b6ecbc5 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/ironlake/acpi.c
@@ -21,7 +21,7 @@
 #include <types.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include "nehalem.h"
+#include "ironlake.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl
index 2b26096be6..2b26096be6 100644
--- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl
+++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl
diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl
index 404801ec3f..659234b4aa 100644
--- a/src/northbridge/intel/nehalem/acpi/nehalem.asl
+++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl
@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include "../nehalem.h"
+#include "../ironlake.h"
 #include "hostbridge.asl"
 #include <southbridge/intel/common/rcba.h>
 
diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 2f9f7da916..2f9f7da916 100644
--- a/src/northbridge/intel/nehalem/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/ironlake/chip.h
index a9d136baad..dad03dac1b 100644
--- a/src/northbridge/intel/nehalem/chip.h
+++ b/src/northbridge/intel/ironlake/chip.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H
-#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H
+#ifndef NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H
+#define NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H
 
 #include <drivers/intel/gma/i915.h>
 
@@ -25,7 +25,7 @@
  *  0x06 = Enabled, 6ms short pulse
  *  0x07 = Enabled, 100ms short pulse
  */
-struct northbridge_intel_nehalem_config {
+struct northbridge_intel_ironlake_config {
 	u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
 	u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
 	u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
@@ -48,4 +48,4 @@ struct northbridge_intel_nehalem_config {
 	u16 pci_mmio_size;
 };
 
-#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */
+#endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index a809121310..fe4ad7feff 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -26,9 +26,9 @@
 #include <cpu/intel/turbo.h>
 #include <arch/cpu.h>
 
-#include "nehalem.h"
+#include "ironlake.h"
 
-static void nehalem_setup_bars(void)
+static void ironlake_setup_bars(void)
 {
 	/* Setting up Southbridge. In the northbridge code. */
 	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
@@ -114,7 +114,7 @@ static void early_cpu_init (void)
 	wrmsr(IA32_MISC_ENABLE, m);
 }
 
-void nehalem_early_initialization(int chipset_type)
+void ironlake_early_initialization(int chipset_type)
 {
 	u32 capid0_a;
 	u8 reg8;
@@ -126,14 +126,14 @@ void nehalem_early_initialization(int chipset_type)
 		reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
 		reg8 &= ~7;	/* Clear 2:0 */
 
-		if (chipset_type == NEHALEM_MOBILE)
+		if (chipset_type == IRONLAKE_MOBILE)
 			reg8 |= 1;	/* Set bit 0 */
 
 		pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
 	}
 
 	/* Setup all BARs required for early PCIe and raminit */
-	nehalem_setup_bars();
+	ironlake_setup_bars();
 
 	s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
 	    (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3);
diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/ironlake/finalize.c
index c03b067cbf..f76124be76 100644
--- a/src/northbridge/intel/nehalem/finalize.c
+++ b/src/northbridge/intel/ironlake/finalize.c
@@ -14,11 +14,11 @@
  * GNU General Public License for more details.
  */
 
-#include "nehalem.h"
+#include "ironlake.h"
 
 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)
 
-void intel_nehalem_finalize_smm(void)
+void intel_ironlake_finalize_smm(void)
 {
 	MCHBAR32_OR(0x5500, 1 << 0);	/* PAVP */
 	MCHBAR32_OR(0x5f00, 1 << 31);	/* SA PM */
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/ironlake/gma.c
index d717e48821..27c0827ead 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/ironlake/gma.c
@@ -33,7 +33,7 @@
 #include <types.h>
 
 #include "chip.h"
-#include "nehalem.h"
+#include "ironlake.h"
 
 /* some vga option roms are used for several chipsets but they only have one
  * PCI ID in their header. If we encounter such an option rom, we need to do
@@ -93,7 +93,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
 
 static void gma_pm_init_post_vbios(struct device *dev)
 {
-	struct northbridge_intel_nehalem_config *conf = dev->chip_info;
+	struct northbridge_intel_ironlake_config *conf = dev->chip_info;
 	u32 reg32;
 
 	printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
@@ -177,7 +177,7 @@ static void gma_func0_init(struct device *dev)
 
 	if (!acpi_is_wakeup_s3() &&
 	    CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
-		struct northbridge_intel_nehalem_config *conf = dev->chip_info;
+		struct northbridge_intel_ironlake_config *conf = dev->chip_info;
 		int lightup_ok;
 		printk(BIOS_SPEW, "Initializing VGA without OPROM.");
 
@@ -223,7 +223,7 @@ intel_gma_get_controller_info(void)
 	if (!dev) {
 		return NULL;
 	}
-	struct northbridge_intel_nehalem_config *chip = dev->chip_info;
+	struct northbridge_intel_ironlake_config *chip = dev->chip_info;
 	return &chip->gfx;
 }
 
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/ironlake/ironlake.h
index 493c5b14cd..aa8cb7f4a6 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
-#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
+#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
+#define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
 
 #ifndef __ASSEMBLER__
 
@@ -99,9 +99,9 @@ typedef struct {
 #define D1F0_VC0RCTL 0x114
 
 /* Chipset types */
-#define NEHALEM_MOBILE	0
-#define NEHALEM_DESKTOP	1
-#define NEHALEM_SERVER	2
+#define IRONLAKE_MOBILE	0
+#define IRONLAKE_DESKTOP	1
+#define IRONLAKE_SERVER	2
 
 /* Device ID for SandyBridge and IvyBridge */
 #define BASE_REV_SNB	0x00
@@ -249,14 +249,14 @@ typedef struct {
 #define PCI_DEVICE_ID_SB 0x0104
 #define PCI_DEVICE_ID_IB 0x0154
 
-void intel_nehalem_finalize_smm(void);
+void intel_ironlake_finalize_smm(void);
 
 int bridge_silicon_revision(void);
-void nehalem_early_initialization(int chipset_type);
-void nehalem_late_initialization(void);
+void ironlake_early_initialization(int chipset_type);
+void ironlake_late_initialization(void);
 void mainboard_pre_raminit(void);
 void mainboard_get_spd_map(u8 *spd_addrmap);
 
 #endif
 #endif
-#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */
+#endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/ironlake/memmap.c
index 5de4b80acf..b2d61fe93a 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/ironlake/memmap.c
@@ -23,7 +23,7 @@
 #include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <cpu/intel/smm_reloc.h>
-#include "nehalem.h"
+#include "ironlake.h"
 
 static uintptr_t smm_region_start(void)
 {
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index 1718307797..fe8eed36c9 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -26,7 +26,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include "chip.h"
-#include "nehalem.h"
+#include "ironlake.h"
 #include <cpu/intel/smm_reloc.h>
 
 static int bridge_revision_id = -1;
@@ -228,7 +228,7 @@ static void northbridge_init(struct device *dev)
 }
 
 /* Disable unused PEG devices based on devicetree before PCI enumeration */
-static void nehalem_init(void *const chip_info)
+static void ironlake_init(void *const chip_info)
 {
 	u32 deven_mask = UINT32_MAX;
 	const struct device *dev;
@@ -287,8 +287,8 @@ static void enable_dev(struct device *dev)
 	}
 }
 
-struct chip_operations northbridge_intel_nehalem_ops = {
+struct chip_operations northbridge_intel_ironlake_ops = {
 	CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge")
 	.enable_dev = enable_dev,
-	.init = nehalem_init,
+	.init = ironlake_init,
 };
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index de02882483..e702e1749e 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -41,7 +41,7 @@
 #include <types.h>
 
 #include "chip.h"
-#include "nehalem.h"
+#include "ironlake.h"
 #include "raminit.h"
 #include "raminit_tables.h"
 
@@ -1362,7 +1362,7 @@ static void program_board_delay(struct raminfo *info)
 static unsigned int get_mmio_size(void)
 {
 	const struct device *dev;
-	const struct northbridge_intel_nehalem_config *cfg = NULL;
+	const struct northbridge_intel_ironlake_config *cfg = NULL;
 
 	dev = pcidev_path_on_root(HOST_BRIDGE);
 	if (dev)
diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/ironlake/raminit.h
index 9a200d475f..1a55407d39 100644
--- a/src/northbridge/intel/nehalem/raminit.h
+++ b/src/northbridge/intel/ironlake/raminit.h
@@ -16,7 +16,7 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
-#include "nehalem.h"
+#include "ironlake.h"
 
 void chipset_init(const int s3resume);
 /* spd_addrmap is array of 4 elements:
diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/ironlake/raminit_tables.c
index 1bd73305ea..1bd73305ea 100644
--- a/src/northbridge/intel/nehalem/raminit_tables.c
+++ b/src/northbridge/intel/ironlake/raminit_tables.c
diff --git a/src/northbridge/intel/nehalem/raminit_tables.h b/src/northbridge/intel/ironlake/raminit_tables.h
index d912d6b18a..d912d6b18a 100644
--- a/src/northbridge/intel/nehalem/raminit_tables.h
+++ b/src/northbridge/intel/ironlake/raminit_tables.h
diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/ironlake/romstage.c
index eceb8c2513..fdd71b486a 100644
--- a/src/northbridge/intel/nehalem/romstage.c
+++ b/src/northbridge/intel/ironlake/romstage.c
@@ -22,12 +22,12 @@
 #include <cpu/x86/lapic.h>
 #include <timestamp.h>
 #include <romstage_handoff.h>
-#include "nehalem.h"
+#include "ironlake.h"
 #include <arch/romstage.h>
 #include <device/pci_def.h>
 #include <device/device.h>
-#include <northbridge/intel/nehalem/chip.h>
-#include <northbridge/intel/nehalem/raminit.h>
+#include <northbridge/intel/ironlake/chip.h>
+#include <northbridge/intel/ironlake/raminit.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <southbridge/intel/ibexpeak/pch.h>
 #include <southbridge/intel/ibexpeak/me.h>
@@ -44,7 +44,7 @@ void mainboard_romstage_entry(void)
 	enable_lapic();
 
 	/* TODO, make this configurable */
-	nehalem_early_initialization(NEHALEM_MOBILE);
+	ironlake_early_initialization(IRONLAKE_MOBILE);
 
 	early_pch_init();
 
diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/ironlake/smi.c
index c3433a39e7..73cd06281b 100644
--- a/src/northbridge/intel/nehalem/smi.c
+++ b/src/northbridge/intel/ironlake/smi.c
@@ -16,7 +16,7 @@
 #include <types.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include "nehalem.h"
+#include "ironlake.h"
 
 #include <cpu/intel/smm_reloc.h>