diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 14:03:44 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:23 +0000 |
| commit | b274ec73ab608384c925876d5a3bcf0396dcc3d5 (patch) | |
| tree | 1eede7603565a8dc1dda075c4aa8b072f5c111c8 /src/northbridge/intel/ironlake/Kconfig | |
| parent | 10f9b83f534bdc89e00f0a02befd952ae8d7f829 (diff) | |
nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhere
Bootblock enabling needs some special handling. Also, the definition of
the `get_pcie_bar` function is incorrect for Ironlake, so remove it.
With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work.
However, it has not been tested. Using 256 busses should still work.
Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/ironlake/Kconfig')
| -rw-r--r-- | src/northbridge/intel/ironlake/Kconfig | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index d371dac729..701c1f92a1 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -18,9 +18,6 @@ config VBOOT # CPU is reset without platform/TPM during romstage select TPM_STARTUP_IGNORE_POSTINIT -config MMCONF_BUS_NUMBER - default 256 - config CBFS_SIZE hex default 0x100000 @@ -47,6 +44,9 @@ config DCACHE_BSP_STACK_SIZE config MMCONF_BASE_ADDRESS default 0xe0000000 +config MMCONF_BUS_NUMBER + default 256 + config INTEL_GMA_BCLV_OFFSET default 0x48254 |