From b274ec73ab608384c925876d5a3bcf0396dcc3d5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 Jan 2021 14:03:44 +0100 Subject: nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhere Bootblock enabling needs some special handling. Also, the definition of the `get_pcie_bar` function is incorrect for Ironlake, so remove it. With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work. However, it has not been tested. Using 256 busses should still work. Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/ironlake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/ironlake/Kconfig') diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index d371dac729..701c1f92a1 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -18,9 +18,6 @@ config VBOOT # CPU is reset without platform/TPM during romstage select TPM_STARTUP_IGNORE_POSTINIT -config MMCONF_BUS_NUMBER - default 256 - config CBFS_SIZE hex default 0x100000 @@ -47,6 +44,9 @@ config DCACHE_BSP_STACK_SIZE config MMCONF_BASE_ADDRESS default 0xe0000000 +config MMCONF_BUS_NUMBER + default 256 + config INTEL_GMA_BCLV_OFFSET default 0x48254 -- cgit v1.2.3