diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-09 14:00:44 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-18 16:00:45 +0000 |
| commit | 799c3219146c8d246ef95f1fdb83dc7bc1f2be61 (patch) | |
| tree | e6dcc99fe3b577d28b602311232779eff8dda4cb /src/northbridge/intel/i440bx | |
| parent | 9cbbba68b650933cf552f9e1b969f08e463c641f (diff) | |
cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Diffstat (limited to 'src/northbridge/intel/i440bx')
| -rw-r--r-- | src/northbridge/intel/i440bx/memmap.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d95268ad..5cee1b4d38 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -8,7 +8,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -39,7 +39,7 @@ void *cbmem_top_chipset(void) * * Source: 440BX datasheet, pages 3-28 thru 3-29. */ - unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; + uintptr_t tom = pci_read_config8(NB, DRB7) * 8 * MiB; int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; /* T_SZ and TSEG_EN */ @@ -48,7 +48,7 @@ void *cbmem_top_chipset(void) int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } void fill_postcar_frame(struct postcar_frame *pcf) |