diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 18:19:29 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 09:59:34 +0000 |
| commit | dd7470cb7ec34478e279476837b73bc70e48476d (patch) | |
| tree | ff0aba55b965a9841007b03ac9260643d2b2631e /src/northbridge/intel/haswell | |
| parent | 45f448f4a4e09b270d964c98d3aced2e73d9d6bc (diff) | |
mb/asrock/b85m_pro4: Factor out common MRC settings
These settings are the same on all boards. Since the other boards
currently overwrite the struct contents, it doesn't make a difference.
To ease review, the same settings will be dropped from other boards in
separate commits, one board at a time.
Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index b2f8e23b71..ee211beab1 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -29,6 +29,18 @@ void mainboard_romstage_entry(void) int wake_from_s3; struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .tseg_size = CONFIG_SMM_TSEG_SIZE, }; mainboard_fill_pei_data(&pei_data); |