From dd7470cb7ec34478e279476837b73bc70e48476d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 18:19:29 +0200 Subject: mb/asrock/b85m_pro4: Factor out common MRC settings These settings are the same on all boards. Since the other boards currently overwrite the struct contents, it doesn't make a difference. To ease review, the same settings will be dropped from other boards in separate commits, one board at a time. Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick --- src/northbridge/intel/haswell/romstage.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index b2f8e23b71..ee211beab1 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -29,6 +29,18 @@ void mainboard_romstage_entry(void) int wake_from_s3; struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .tseg_size = CONFIG_SMM_TSEG_SIZE, }; mainboard_fill_pei_data(&pei_data); -- cgit v1.2.3