diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-27 21:13:44 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-02 21:56:00 +0000 |
| commit | 6237175ed5ef29a0e9b82cc7268ca424c5bb44ea (patch) | |
| tree | 4f60ba095f7716baa777e7b93305c16418915d4a /src/northbridge/intel/haswell/registers/dmibar.h | |
| parent | 9fa141898e49a844864cfc00f1ddc4c4e1981c2a (diff) | |
nb/intel/haswell: Uniformize include guards
Remove leading and trailing underscores and change `RAMINIT_H` to be
more consistent with other headers.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/registers/dmibar.h')
| -rw-r--r-- | src/northbridge/intel/haswell/registers/dmibar.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/registers/dmibar.h b/src/northbridge/intel/haswell/registers/dmibar.h index 9d523825a7..09a9078353 100644 --- a/src/northbridge/intel/haswell/registers/dmibar.h +++ b/src/northbridge/intel/haswell/registers/dmibar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_REGISTERS_DMIBAR_H__ -#define __HASWELL_REGISTERS_DMIBAR_H__ +#ifndef HASWELL_REGISTERS_DMIBAR_H +#define HASWELL_REGISTERS_DMIBAR_H #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ @@ -53,4 +53,4 @@ #define DMI_AFE_PM_TMR 0xc28 /* 32bit */ -#endif /* __HASWELL_REGISTERS_DMIBAR_H__ */ +#endif /* HASWELL_REGISTERS_DMIBAR_H */ |