From 6237175ed5ef29a0e9b82cc7268ca424c5bb44ea Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 27 Mar 2021 21:13:44 +0100 Subject: nb/intel/haswell: Uniformize include guards Remove leading and trailing underscores and change `RAMINIT_H` to be more consistent with other headers. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/registers/dmibar.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/haswell/registers/dmibar.h') diff --git a/src/northbridge/intel/haswell/registers/dmibar.h b/src/northbridge/intel/haswell/registers/dmibar.h index 9d523825a7..09a9078353 100644 --- a/src/northbridge/intel/haswell/registers/dmibar.h +++ b/src/northbridge/intel/haswell/registers/dmibar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_REGISTERS_DMIBAR_H__ -#define __HASWELL_REGISTERS_DMIBAR_H__ +#ifndef HASWELL_REGISTERS_DMIBAR_H +#define HASWELL_REGISTERS_DMIBAR_H #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ @@ -53,4 +53,4 @@ #define DMI_AFE_PM_TMR 0xc28 /* 32bit */ -#endif /* __HASWELL_REGISTERS_DMIBAR_H__ */ +#endif /* HASWELL_REGISTERS_DMIBAR_H */ -- cgit v1.2.3