diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 20:48:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-23 10:59:26 +0000 |
| commit | c4ee714881c7f7bb7a9208b39c76d98578c434b1 (patch) | |
| tree | bbf6051210754cd954b792163d2331eb0bf309bc /src/northbridge/intel/haswell/raminit.c | |
| parent | d99b693c965abb13aa57c5701bfd08547fa93cb5 (diff) | |
nb/intel/haswell: Use unshifted SPD addresses in mainboards
It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/raminit.c')
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index d84d3fb12a..1f84ffa5cb 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -347,8 +347,11 @@ void perform_raminit(const int s3resume) struct spd_info spdi = {0}; mb_get_spd_map(&spdi); - for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) - pei_data.spd_addresses[i] = spdi.addresses[i]; + /* MRC expects left-aligned SMBus addresses, and 0xff for memory-down */ + for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) { + const uint8_t addr = spdi.addresses[i]; + pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0xff : addr << 1; + } /* Calculate unimplemented DIMM slots for each channel */ pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); |