From c4ee714881c7f7bb7a9208b39c76d98578c434b1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 12 Mar 2021 20:48:53 +0100 Subject: nb/intel/haswell: Use unshifted SPD addresses in mainboards It's common to use the raw, unshifted I2C address in coreboot. Adapt mainboards accordingly and perform the shift in MRC glue code. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458 Reviewed-by: Nico Huber Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/raminit.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/haswell/raminit.c') diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index d84d3fb12a..1f84ffa5cb 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -347,8 +347,11 @@ void perform_raminit(const int s3resume) struct spd_info spdi = {0}; mb_get_spd_map(&spdi); - for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) - pei_data.spd_addresses[i] = spdi.addresses[i]; + /* MRC expects left-aligned SMBus addresses, and 0xff for memory-down */ + for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) { + const uint8_t addr = spdi.addresses[i]; + pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0xff : addr << 1; + } /* Calculate unimplemented DIMM slots for each channel */ pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); -- cgit v1.2.3