diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-22 12:28:07 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-01-27 22:48:06 +0100 |
| commit | f1e3c763b3eef15dbfae73f485408a0dec230d00 (patch) | |
| tree | 28682b0d4ad36063b3612c8a774af868a3e55878 /src/northbridge/intel/haswell/ram_calc.c | |
| parent | 91fac61240612291f7be3362f7acad31803e8b03 (diff) | |
CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.
TODO: Check TSEG alignment, it used for MTRR programming.
Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/haswell/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/haswell/ram_calc.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index 99e7d672b9..01ad50de85 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -24,12 +24,17 @@ #include <cbmem.h> #include "haswell.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Base of TSEG is top of usable DRAM below 4GiB. The register has * 1 MiB alignement. */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom & ~((1 << 20) - 1); + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom & ~((1 << 20) - 1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); } |