diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 23:44:30 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 13:06:11 +0000 |
| commit | 79e3a1f8a5c50d27948cb05310989b4e28f3f74c (patch) | |
| tree | d6c5754c1767251c009e553097ca6cc0edceaac5 /src/northbridge/intel/haswell/acpi/hostbridge.asl | |
| parent | e339f9505bbf24ba41c37e4277456acad255d09a (diff) | |
nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`
Tested with BUILD_TIMELESS=1, Google Wolf remains identical.
Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/acpi/hostbridge.asl')
| -rw-r--r-- | src/northbridge/intel/haswell/acpi/hostbridge.asl | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index f0cb86bd26..3e617ecbb9 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "../haswell.h" +#include <southbridge/intel/common/rcba.h> + Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -167,3 +170,35 @@ Method (_CRS, 0, Serialized) /* Configurable TDP */ #include "ctdp.asl" + +/* PCI Express Graphics */ +#include "peg.asl" + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + +#if CONFIG(CHROMEOS_RAMOOPS) + Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) +#endif + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return (PDRS) + } +} |