nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`

Tested with BUILD_TIMELESS=1, Google Wolf remains identical.

Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 42 insertions, 42 deletions

diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl
index ea6dde65c1..bba5c2e593 100644
--- a/src/mainboard/asrock/b85m_pro4/dsdt.asl
+++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl
@@ -20,7 +20,7 @@ DefinitionBlock(
 
 	Device (\_SB.PCI0)
 	{
-		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl
index dd55ba8bbd..d3e7ba17d0 100644
--- a/src/mainboard/asrock/h81m-hds/dsdt.asl
+++ b/src/mainboard/asrock/h81m-hds/dsdt.asl
@@ -20,7 +20,7 @@ DefinitionBlock(
 	{
 		Device (PCI0)
 		{
-		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl
index 07a1d03fca..45442db902 100644
--- a/src/mainboard/google/beltino/dsdt.asl
+++ b/src/mainboard/google/beltino/dsdt.asl
@@ -24,7 +24,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
+			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		}
 	}
diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl
index 71b7863ac2..8ca683dcb2 100644
--- a/src/mainboard/google/slippy/dsdt.asl
+++ b/src/mainboard/google/slippy/dsdt.asl
@@ -24,7 +24,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
+			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl
index 7fdd69bc60..5971917f9d 100644
--- a/src/mainboard/intel/baskingridge/dsdt.asl
+++ b/src/mainboard/intel/baskingridge/dsdt.asl
@@ -24,7 +24,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
+			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl
index 426d8017ed..9a54673ec8 100644
--- a/src/mainboard/lenovo/t440p/dsdt.asl
+++ b/src/mainboard/lenovo/t440p/dsdt.asl
@@ -24,7 +24,7 @@ DefinitionBlock(
 
 	Device (\_SB.PCI0)
 	{
-		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 	}
diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl
index 08a26ab088..f8e9884f3f 100644
--- a/src/mainboard/supermicro/x10slm-f/dsdt.asl
+++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl
@@ -19,7 +19,7 @@ DefinitionBlock(
 
 	Device (\_SB.PCI0)
 	{
-		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
 		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl
deleted file mode 100644
index 57344abc1d..0000000000
--- a/src/northbridge/intel/haswell/acpi/haswell.asl
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "../haswell.h"
-#include "hostbridge.asl"
-#include "peg.asl"
-#include <southbridge/intel/common/rcba.h>
-
-/* PCI Device Resource Consumption */
-Device (PDRC)
-{
-	Name (_HID, EISAID ("PNP0C02"))
-	Name (_UID, 1)
-
-	Name (PDRS, ResourceTemplate () {
-		Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000)
-		Memory32Fixed (ReadWrite, DEFAULT_MCHBAR,   0x00008000)
-		Memory32Fixed (ReadWrite, DEFAULT_DMIBAR,   0x00001000)
-		Memory32Fixed (ReadWrite, DEFAULT_EPBAR,    0x00001000)
-		Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
-		Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
-		Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
-		Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
-
-#if CONFIG(CHROMEOS_RAMOOPS)
-		Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
-					  CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
-#endif
-	})
-
-	// Current Resource Settings
-	Method (_CRS, 0, Serialized)
-	{
-		Return (PDRS)
-	}
-}
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index f0cb86bd26..3e617ecbb9 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "../haswell.h"
+#include <southbridge/intel/common/rcba.h>
+
 Name (_HID, EISAID ("PNP0A08"))	// PCIe
 Name (_CID, EISAID ("PNP0A03"))	// PCI
 
@@ -167,3 +170,35 @@ Method (_CRS, 0, Serialized)
 
 /* Configurable TDP */
 #include "ctdp.asl"
+
+/* PCI Express Graphics */
+#include "peg.asl"
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+	Name (_HID, EISAID ("PNP0C02"))
+	Name (_UID, 1)
+
+	Name (PDRS, ResourceTemplate () {
+		Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000)
+		Memory32Fixed (ReadWrite, DEFAULT_MCHBAR,   0x00008000)
+		Memory32Fixed (ReadWrite, DEFAULT_DMIBAR,   0x00001000)
+		Memory32Fixed (ReadWrite, DEFAULT_EPBAR,    0x00001000)
+		Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
+		Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+		Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+		Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
+
+#if CONFIG(CHROMEOS_RAMOOPS)
+		Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+					  CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
+#endif
+	})
+
+	// Current Resource Settings
+	Method (_CRS, 0, Serialized)
+	{
+		Return (PDRS)
+	}
+}