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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-05 15:41:09 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-02-05 07:56:48 +0000 |
| commit | 7261b5ade5c2035da026837afdb20a7ec1252b19 (patch) | |
| tree | e1daa5ec08b97a3a18f33057eb8373080146d448 /src/northbridge/intel/gm45 | |
| parent | 7aea15aa6b59c96a6d4c0c847352dd1c45145c7c (diff) | |
cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER
Leftover from using UDELAY_LAPIC on these platforms.
Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/romstage.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index b87380a076..744c92bd70 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/lapic.h> #include <arch/romstage.h> #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> @@ -42,8 +41,6 @@ void mainboard_romstage_entry(void) /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); - enable_lapic(); - /* First, run everything needed for console output. */ i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); |