From 7261b5ade5c2035da026837afdb20a7ec1252b19 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sat, 5 Jun 2021 15:41:09 +0300
Subject: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER
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Leftover from using UDELAY_LAPIC on these platforms.

Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
 src/northbridge/intel/gm45/romstage.c | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'src/northbridge/intel/gm45')

diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index b87380a076..744c92bd70 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -5,7 +5,6 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <acpi/acpi.h>
-#include <cpu/x86/lapic.h>
 #include <arch/romstage.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
@@ -42,8 +41,6 @@ void mainboard_romstage_entry(void)
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
-	enable_lapic();
-
 	/* First, run everything needed for console output. */
 	i82801ix_early_init();
 	setup_pch_gpios(&mainboard_gpio_map);
-- 
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