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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-06-25 18:37:45 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-11-15 02:44:10 +0100
commit11739a48ce08d1ef11bfd54670ec23a1ee6daccd (patch)
treec76c1e0ae5fe05e8fbe4ef30dc41cedeeeb2121a /src/northbridge/amd/amdmct
parent9426e4fcf5f49c46fa1e5cbe9fc38d2575cfdb62 (diff)
northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
AMD Opteron processors contain a very fragile phy phase detection circuit. Additionally, the algorithm given in the BKDG does not function as intended; this was verified both on real hardware via execution trace and on paper with values read back from multiple CPUs and DIMMs. As a result, the phy training algorithm given in the BKDG has been replaced with a phy training algorithm developed at Raptor Engineering. This particular patch is the first part of that algorithm; the code is updated in future patches but this should exist in the historical record in case something breaks down in the later sections of code. Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12007 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index 496803e94b..dfddb60609 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -203,6 +203,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
pDCTData->WLCriticalGrossDelayPrevPass = cgd;
+ if (pDCTstat->Speed != pDCTstat->TargetFreq) {
+ /* FIXME
+ * Using the Pass 1 training values causes major phy training problems on
+ * all Family 15h processors I tested (Pass 1 values are randomly too high,
+ * and Pass 2 cannot lock).
+ * Figure out why this is and fix it, then remove the bypass code below...
+ */
+ if (pass == FirstPass) {
+ for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
+ pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane];
+ pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane];
+ }
+ return 0;
+ }
+ }
+
/* Compensate for occasional noise/instability causing sporadic training failure */
for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
uint8_t faulty_value_detected = 0;