diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-07-26 00:55:43 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-16 17:55:57 +0100 |
| commit | f682d0028cb33fc4a085af83344f4a7b9c0e78f2 (patch) | |
| tree | 84c2289b2ca976c728f2fb42ded31c9f79c7a275 /src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | |
| parent | 474ff3dee54e81017587f53ce644307e4f655333 (diff) | |
amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Sufficient support has been added to allow booting with registered
DIMMs on the KGPE-D16 in certain slots. ECC support needs additional
work; the ECC data lanes appear to cause boot failures in some slots.
Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12017
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index e5636e2f33..c85dc2721f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1740,6 +1740,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, u16 EccDQSLike; u8 EccDQSScale; u32 val, val0, val1; + int16_t delay_differential; EccDQSLike = pDCTstat->CH_EccDQSLike[Channel]; EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; @@ -1749,14 +1750,22 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, u16 *p; p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; - /* DQS Delay Value of Data Bytelane - * most like ECC byte lane */ - val0 = p[EccDQSLike & 0x07]; - /* DQS Delay Value of Data Bytelane - * 2nd most like ECC byte lane */ - val1 = p[(EccDQSLike>>8) & 0x07]; + if (pDCTstat->Status & (1 << SB_Registered)) { + val0 = p[0x2]; + val1 = p[0x3]; + + delay_differential = (int16_t)val1 - (int16_t)val0; + delay_differential += (int16_t)val1; + + val = delay_differential; + } else { + /* DQS Delay Value of Data Bytelane + * most like ECC byte lane */ + val0 = p[EccDQSLike & 0x07]; + /* DQS Delay Value of Data Bytelane + * 2nd most like ECC byte lane */ + val1 = p[(EccDQSLike>>8) & 0x07]; - if (!(pDCTstat->Status & (1 << SB_Registered))) { if(val0 > val1) { val = val0 - val1; } else { @@ -1771,9 +1780,6 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, } else { val += val0; } - } else { - val = val1 - val0; - val += val1; } pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; |