diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-03-27 22:50:09 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-01 21:14:30 +0200 |
| commit | 620fa5f30fb0c78bb51aef2dae3a5694ac2c3c87 (patch) | |
| tree | 0ca715cdf913b34e96c2327c0cd8248ad28e9b1d /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
| parent | d5c82afa37f99a6db8ebb06d0e3c4c0ad4e488db (diff) | |
northbridge/amd/amdfam10: Collect DIMM information for ramstage use
1.) Allow MCT information structures to be copied to cbmem.
2.) Retrieve DIMM vendor, model, and serial information.
3.) Allow maximum installable memory to be set via devicetree.
Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9137
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 770b663fe9..0f4dd43642 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -2030,7 +2031,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, * DATAAload=number of ranks on the "A" bus slots. * DATABload=number of ranks on the "B" bus slots. */ - u16 i, j; + u16 i, j, k; u8 smbaddr; u8 SPDCtrl; u16 RegDIMMPresent, MaxDimms; @@ -2077,10 +2078,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid |= 1 << i; } } + /* Get module information for SMBIOS */ + if (pDCTstat->DIMMValid & (1 << i)) { + pDCTstat->DimmManufacturerID[i] = 0; + for (k = 0; k < 8; k++) + pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); + for (k = 0; k < SPD_PARTN_LENGTH; k++) + pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); + pDCTstat->DimmRevisionNumber[i] = 0; + for (k = 0; k < 2; k++) + pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); + pDCTstat->DimmSerialNumber[i] = 0; + for (k = 0; k < 4; k++) + pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); + pDCTstat->DimmRows[i] = (mctRead_SPD(smbaddr, SPD_Addressing) & 0x38) >> 3; + pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_Addressing) & 0x7; + pDCTstat->DimmRanks[i] = ((mctRead_SPD(smbaddr, SPD_Organization) & 0x38) >> 3) + 1; + pDCTstat->DimmBanks[i] = 1ULL << (((mctRead_SPD(smbaddr, SPD_Density) & 0x70) >> 4) + 3); + pDCTstat->DimmWidth[i] = 1ULL << ((mctRead_SPD(smbaddr, SPD_BusWidth) & 0x7) + 3); + } /* Check module type */ byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE) & 0x7; - if (byte == JED_RDIMM || byte == JED_MiniRDIMM) + if (byte == JED_RDIMM || byte == JED_MiniRDIMM) { RegDIMMPresent |= 1 << i; + pDCTstat->DimmRegistered[i] = 1; + } + else { + pDCTstat->DimmRegistered[i] = 0; + } /* Check ECC capable */ byte = mctRead_SPD(smbaddr, SPD_BusWidth); if (byte & JED_ECC) { |