diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2008-01-18 15:08:58 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2008-01-18 15:08:58 +0000 |
| commit | f8ee1806ac524bc782c93eccc59ee3c929abddb9 (patch) | |
| tree | 7daab6b3aa82476a10d38fbf68068f4a409d2ce9 /src/northbridge/amd/amdmct/mct | |
| parent | 7e61e45402aba2b90997f4f02ca8266cf65a229a (diff) | |
Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctmtr_d.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index c0839d2a88..d39bfcc8b2 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -75,7 +75,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, Set default values for CPU registers ======================================================================*/ - /* NOTE : For LinuxBIOS, we don't need to set mtrr enables here because + /* NOTE : For coreboot, we don't need to set mtrr enables here because they are still enable from cache_as_ram.inc */ addr = 0x250; @@ -88,7 +88,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /*====================================================================== Set variable MTRR values ======================================================================*/ - /* NOTE: for LinuxBIOS change from 0x200 to 0x204: LinuxBIOS is using + /* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using 0x200, 0x201 for [1M, CONFIG_TOP_MEM) 0x202, 0x203 for ROM Caching */ |