From f8ee1806ac524bc782c93eccc59ee3c929abddb9 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 18 Jan 2008 15:08:58 +0000 Subject: Rename almost all occurences of LinuxBIOS to coreboot. Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/mct/mctmtr_d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/amd/amdmct/mct') diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index c0839d2a88..d39bfcc8b2 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -75,7 +75,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, Set default values for CPU registers ======================================================================*/ - /* NOTE : For LinuxBIOS, we don't need to set mtrr enables here because + /* NOTE : For coreboot, we don't need to set mtrr enables here because they are still enable from cache_as_ram.inc */ addr = 0x250; @@ -88,7 +88,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /*====================================================================== Set variable MTRR values ======================================================================*/ - /* NOTE: for LinuxBIOS change from 0x200 to 0x204: LinuxBIOS is using + /* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using 0x200, 0x201 for [1M, CONFIG_TOP_MEM) 0x202, 0x203 for ROM Caching */ -- cgit v1.2.3