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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-09-05 18:56:05 -0500
committerMartin Roth <martinroth@google.com>2015-11-02 23:26:41 +0100
commit2a83935d9f50e3059e7747338a700c2fceb1731a (patch)
treeb40831293a339c6743ec86e7820111c38c536113 /src/northbridge/amd/amdfam10/acpi.c
parent65eec4d959a847c43b5f4e92c6eee60f042fd7f6 (diff)
northbridge/amd/amdfam10: Set DIMM voltage based on SPD data
Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11957 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/amd/amdfam10/acpi.c')
-rw-r--r--src/northbridge/amd/amdfam10/acpi.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c
index 5ff38aab49..ad54abd765 100644
--- a/src/northbridge/amd/amdfam10/acpi.c
+++ b/src/northbridge/amd/amdfam10/acpi.c
@@ -303,8 +303,7 @@ void northbridge_acpi_write_vars(device_t device)
} else {
if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
CBST = (u8) (0x0f);
- }
- else {
+ } else {
CBST = (u8) (0x00);
}
}