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authorSerin Yeh <serin.yeh@intel.corp-partner.google.com>2023-09-27 17:36:18 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-10-04 09:37:46 +0000
commitab6f016a43cf7d2667f5648dad72ca3d0df03d58 (patch)
treef2eb2eb8752ae3d4fff938dba2dd2d1ac7a7e5d3 /src/mainboard
parentde61edde1b340b245139b3dc89f1f205fb1a1994 (diff)
mb/google/brya/var/yavilla: Add VCM power control sequence
Add VCM power control to configure 2.8V and reset pin, and VCM can be powered on/off properly. BUG=b:292907385 TEST=Run ITS test Change-Id: I242025836fd50076a40ffcc4e5d4a5d5bc6fb4d0 Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78170 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/brya/variants/yavilla/overridetree.cb21
1 files changed, 18 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index d31a8f99fa..ee5a3b6b6a 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -375,12 +375,11 @@ chip soc/intel/alderlake
register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L
#_ON
- register "on_seq.ops_cnt" = "5"
+ register "on_seq.ops_cnt" = "4"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
- register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
- register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
#_OFF
register "off_seq.ops_cnt" = "4"
@@ -400,6 +399,22 @@ chip soc/intel/alderlake
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
register "vcm_compat" = ""dongwoon,dw9714""
+ register "has_power_resource" = "1"
+ register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+ #Controls
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_D3" # WCAM_RST_L
+
+ #_ON
+ register "on_seq.ops_cnt" = "2"
+ register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "2"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+ register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
device i2c 0C on
probe WFC WFC_MIPI_OVTI8856