diff options
| author | Jian Tong <tongjian@huaqin.corp-partner.google.com> | 2024-09-09 14:23:59 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-25 12:28:45 +0000 |
| commit | 42a6c0c24d4cd6a57479cdedd78cdd85312573e7 (patch) | |
| tree | cd67358a4f0398dd53ce32719524cfc3dc5129bf /src/mainboard | |
| parent | 658e274b9f19663651882e41b1bc114e85186ffa (diff) | |
mb/google/brox/var/lotso: Add RTS522A vdd ctrl by GPP_A17
For next DVT build, hw adds this power ctrl.
BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84254
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brox/variants/lotso/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brox/variants/lotso/overridetree.cb | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c index 0b98286224..d5abe8cbe9 100644 --- a/src/mainboard/google/brox/variants/lotso/gpio.c +++ b/src/mainboard/google/brox/variants/lotso/gpio.c @@ -7,6 +7,8 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* GPP_D03 : [] ==> EN_PP3300_SD */ + PAD_CFG_GPO_LOCK(GPP_A17, 1, LOCK_CONFIG), /* GPP_B14 : [NF1: SPKR NF2: TIME_SYNC1 NF4: SATA_LED# NF5: ISH_GP6 * NF6: USB_C_GPP_B14] ==> ACZ_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 1e93c7908f..6678b84312 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -360,6 +360,7 @@ chip soc/intel/alderlake .pcie_rp_aspm = ASPM_L1, }" chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A17)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "enable_delay_ms" = "1" register "srcclk_pin" = "3" |