mb/google/brox/var/lotso: Update cpu power limits

When battery not present, increase PL4 limit from 9 to 40.
Get PL setting from internal thermal and power team.
AC+DC/DC:
PL1=15W
PL2=25W
PL4=114W

AC ONLY:
PL1=15W
PL2=25W
PL4=40W

BUG=b:355094551
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Confirm on lotso EVT board, as expected.

Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84202
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 48 insertions, 3 deletions

diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 175cf019d5..29b4b51ed3 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -117,7 +117,8 @@ config DRIVER_TPM_I2C_BUS
 
 config PL4_LIMIT_FOR_CRITICAL_BAT_BOOT
 	int
-	default 9
+	default 9 if BOARD_GOOGLE_BROX
+	default 40 if BOARD_GOOGLE_LOTSO
 	help
 	  Select this if the variant has to boot even with low battery, critical battery
 	  threshold, or when the battery is physically disconnected. PL4, which stands for
diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk
index c88fed9e39..3754e0dae2 100644
--- a/src/mainboard/google/brox/variants/lotso/Makefile.mk
+++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk
@@ -5,3 +5,4 @@ romstage-y += memory.c
 romstage-y += gpio.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index 79bdb260ad..1e93c7908f 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -74,8 +74,8 @@ chip soc/intel/alderlake
 
 	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
 		.tdp_pl1_override = 15,
-		.tdp_pl2_override = 40,
-		.tdp_pl4 = 57,
+		.tdp_pl2_override = 25,
+		.tdp_pl4 = 114,
 	}"
 
 	device domain 0 on
diff --git a/src/mainboard/google/brox/variants/lotso/ramstage.c b/src/mainboard/google/brox/variants/lotso/ramstage.c
new file mode 100644
index 0000000000..80276607be
--- /dev/null
+++ b/src/mainboard/google/brox/variants/lotso/ramstage.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+
+const struct cpu_power_limits performance_efficient_limits[] = {
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_3,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 25000,
+		.pl2_max_power = 25000,
+		.pl4_power = 114000
+	},
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_4,
+		.cpu_tdp = 15,
+		.pl1_min_power = 15000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 25000,
+		.pl2_max_power = 25000,
+		.pl4_power = 114000
+	},
+};
+
+void __weak variant_devtree_update(void)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+	const struct cpu_power_limits *limits = performance_efficient_limits;
+	size_t limits_size = ARRAY_SIZE(performance_efficient_limits);
+
+	variant_update_power_limits(limits, limits_size);
+}