diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-03-09 13:42:45 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-12 07:40:45 +0000 |
| commit | 396bb46e7dc14a5feb99de4513a13881de9ef83f (patch) | |
| tree | 11b90a4fe2d304922bd3e3c537087f73987173ff /src/mainboard | |
| parent | 84b4882b99e92665ea6db933f8180b489b1759b4 (diff) | |
mb/google/volteer: configure L1Substate for PCIe
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report
issue id #1409566330
BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/volteer/variants/ripto/overridetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb index 32204c58e7..162f93bdb7 100644 --- a/src/mainboard/google/volteer/variants/ripto/overridetree.cb +++ b/src/mainboard/google/volteer/variants/ripto/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/tigerlake + # NVMe warm reboot workaround + # Limit L1.1 (value:2) for RP9, RP11 + register "PcieRpL1Substates[8]" = "2" + register "PcieRpL1Substates[10]" = "2" + device domain 0 on end |