From 396bb46e7dc14a5feb99de4513a13881de9ef83f Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 9 Mar 2020 13:42:45 -0700 Subject: mb/google/volteer: configure L1Substate for PCIe Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround. Reference: #613582 Tiger Lake PCH-LP Sightings Report issue id #1409566330 BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe Signed-off-by: Wonkyu Kim Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413 Tested-by: build bot (Jenkins) Reviewed-by: Srinidhi N Kaushik Reviewed-by: Nick Vaccaro --- src/mainboard/google/volteer/variants/ripto/overridetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb index 32204c58e7..162f93bdb7 100644 --- a/src/mainboard/google/volteer/variants/ripto/overridetree.cb +++ b/src/mainboard/google/volteer/variants/ripto/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/tigerlake + # NVMe warm reboot workaround + # Limit L1.1 (value:2) for RP9, RP11 + register "PcieRpL1Substates[8]" = "2" + register "PcieRpL1Substates[10]" = "2" + device domain 0 on end -- cgit v1.2.3