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authorKevin Chiu <Kevin.Chiu@quantatw.com>2020-06-29 21:31:33 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-07-01 05:22:56 +0000
commit24e62217060b56e75cea67d17d251180eb0ad447 (patch)
tree8a0797e0a5c10e1a65549b5ee8a45ba9333c9c7a /src/mainboard
parent72afe02cfc38b888d4666dbb97b846afea30b009 (diff)
mb/google/zork: update G2 TS RST delay time
in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even rst delay time already meets spec definition: 10us (minimum). Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine on those specific m/b+BOE(G2 TS) panel. BUG=b:159510906 BRANCH=master TEST=emerge-zork coreboot boot with G2 TS, make sure G2 TS is functional Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/zork/variants/berknip/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb
index 18288ec203..229469eda7 100644
--- a/src/mainboard/google/zork/variants/berknip/overridetree.cb
+++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb
@@ -93,7 +93,7 @@ chip soc/amd/picasso
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
- register "generic.reset_delay_ms" = "1"
+ register "generic.reset_delay_ms" = "50"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end