Tyan update for ROM_IMAGE_SIZE > 64K

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 55 insertions, 48 deletions

diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index 2bdabea244..5b8ad9c3fa 100644
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -43,26 +43,27 @@ if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
+
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c" 
-	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+        depends "$(MAINBOARD)/failover.c ./romcc"
+        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "./failover.E ./romcc"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+        depends "$(MAINBOARD)/failover.c ./romcc"
+        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h " 
-	action	"$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+makerule ./auto.E
+        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
-makerule ./auto.inc 
-	depends "./auto.E ./romcc"
-	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+makerule ./auto.inc
+        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -199,8 +200,8 @@ chip northbridge/amd/amdk8
 				device pci 1.3 on end
 				device pci 1.5 on end
 				device pci 1.6 off end
-#                                register "ide0_enable" = "1"
-#                                register "ide1_enable" = "1"
+                                register "ide0_enable" = "1"
+                                register "ide1_enable" = "1"
 			end
 		end #  device pci 18.0 
 		
diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb
index 97238b80e9..520fde347c 100644
--- a/src/mainboard/tyan/s2885/Options.lb
+++ b/src/mainboard/tyan/s2885/Options.lb
@@ -45,6 +45,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
 
 
 ###
@@ -82,7 +84,7 @@ default HARD_RESET_FUNCTION=0
 ## Build code to export a programmable irq routing table
 ##
 default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
@@ -165,6 +167,11 @@ default CC="gcc"
 default HOSTCC="gcc"
 
 ##
+## Disable the gdb stub by default
+## 
+default CONFIG_GDB_STUB=0
+
+##
 ## The Serial Console
 ##
 
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c
index 5065629e0d..b5766c166a 100644
--- a/src/mainboard/tyan/s2885/auto.c
+++ b/src/mainboard/tyan/s2885/auto.c
@@ -56,28 +56,22 @@ static void soft2_reset(void)
 
 static void memreset_setup(void)
 {
-#if 0
    if (is_cpu_pre_c0()) {
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
    }
    else {
-#endif
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-#if 0
    }
-#endif
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
-#if 0
    if (is_cpu_pre_c0()) {
         udelay(800);
         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
         udelay(90);
    }
-#endif
 }
 
 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@@ -123,7 +117,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 	};
 
 	if(maxnodes>2) {
-//		print_debug("this mainboard is only designed for 2 cpus\r\n");
+		print_debug("this mainboard is only designed for 2 cpus\r\n");
 		maxnodes=2;
 	}
 
@@ -150,7 +144,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
-#include "resourcemap.c" /* tyan does not want the default */
+/* tyan does not want the default */
+#include "resourcemap.c" 
 
 #define FIRST_CPU  1
 #define SECOND_CPU 1
@@ -205,7 +200,7 @@ static void main(unsigned long bist)
         	init_timer();
 	
 	        if (cpu_init_detected()) {
-#if 0
+#if 1
         	        asm volatile ("jmp __cpu_reset");
 #else           
                 /* cpu reset also reset the memtroller ????
diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c
index 4c3c4a3a14..a51278b06a 100644
--- a/src/mainboard/tyan/s2885/mainboard.c
+++ b/src/mainboard/tyan/s2885/mainboard.c
@@ -269,6 +269,5 @@ static void enable_dev(struct device *dev)
 	dev_root.ops = &mainboard_operations;
 }
 struct chip_operations mainboard_tyan_s2885_ops = {
-	.name      = "Tyan s2885 mainboard ",
 	.enable_dev = enable_dev, 
 };
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index 319883a160..ba7bc390ad 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -13,10 +13,12 @@ void *smp_write_config_table(void *v)
 
         unsigned char bus_num;
         unsigned char bus_isa;
+	unsigned char bus_8131_0;
         unsigned char bus_8131_1;
         unsigned char bus_8131_2;
 	unsigned char bus_8111_0;
         unsigned char bus_8111_1;
+	unsigned char bus_8151_0;
 	unsigned char bus_8151_1;
 
 
@@ -42,56 +44,59 @@ void *smp_write_config_table(void *v)
        {
                 device_t dev;
 
+		/* 8151 */
+		bus_8151_0 = 1;
+                dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
+                if (dev) {
+                        bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+//                        printk_debug("bus_8151_1=%d\n",bus_8151_1);
+			bus_8111_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_8111_0++;
+			bus_8131_0 = bus_8111_0;
+//			printk_debug("bus_8111_0=%d\n",bus_8111_0);
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+                        bus_8151_1 = 2;
+			bus_8111_0 = bus_8131_0 = 3;
+                }
+
                 /* 8111 */
-                dev = dev_find_slot(3, PCI_DEVFN(0x03,0));
+                dev = dev_find_slot(bus_8111_0, PCI_DEVFN(0x03,0));
                 if (dev) {
-			bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
                         bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                         bus_isa++;
-			printk_debug("bus_isa=%d\n",bus_isa);
+//			printk_debug("bus_isa=%d\n",bus_isa);
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 3:03.0, using defaults\n");
+                        printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
 
                         bus_8111_1 = 6;
                         bus_isa = 7;
                 }
                 /* 8131-1 */
-                dev = dev_find_slot(3, PCI_DEVFN(0x01,0));
+                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
                 if (dev) {
                         bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 3:01.0, using defaults\n");
+                        printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
 
                         bus_8131_1 = 4;
                 }
                 /* 8131-2 */
-                dev = dev_find_slot(3, PCI_DEVFN(0x02,0));
+                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
                 if (dev) {
                         bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 3:02.0, using defaults\n");
+                        printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
 
                         bus_8131_2 = 5;
                 }
-	               /* 8151 */
-                dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
-                if (dev) {
-                        bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        printk_debug("bus_8151_1=%d\n",bus_8151_1);
-   
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
-
-                        bus_8151_1 = 2;
-                }
-  
    
         }
 
@@ -105,18 +110,18 @@ void *smp_write_config_table(void *v)
         smp_write_bus(mc, bus_isa, "ISA   ");
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+	smp_write_ioapic(mc, 2, 0x11, 0xfec00000); //8111
         {
                 device_t dev;
 		struct resource *res;
-                dev = dev_find_slot(3, PCI_DEVFN(0x1,1));
+                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x1,1));
                 if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_0);
 			if (res) {
-				smp_write_ioapic(mc, 0x03, 0x11, res->base);
+				smp_write_ioapic(mc, 3, 0x11, res->base);
 			}
                 }
-                dev = dev_find_slot(3, PCI_DEVFN(0x2,1));
+                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x2,1));
                 if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_0);
 			if (res) {